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january 2013 i ? 2013 microsemi corporation proasic3 nano flash fpgas features and benefits wide range of features ? 10 k to 250 k system gates ? up to 36 kbits of true dual-port sram ? up to 71 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal (6 copper), flash-based cmos process ? instant on level 0 support ? single-chip solution ? retains programmed design when powered off high performance ? 350 mhz system performance in-system programming (isp) and security ? isp using on-chip 128-bit advanced encryption standard (aes) decryption via jt ag (ieee 1532?compliant) ? ? flashlock ? designed to secure fpga contents low power ? low power proasic ? 3 nano products ? 1.5 v core voltage for low power ? support for 1.5 v-only systems ? low-impedance flash switches high-performance r outing hierarchy ? segmented, hierarchical routing and clock structure advanced i/os ? 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?up to 4 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v / 1.8 v / 1.5 v ? wide range power supply voltage support per jesd8-b, allowing i/os to operate from 2.7 v to 3.6 v ? i/o registers on input, output, and enable paths ? selectable schmitt trigger inputs ? hot-swappable and cold-sparing i/os ? programmable output slew rate ? and drive strength ? weak pull-up/-down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible packages across the proasic3 family clock conditioning circuit (ccc) and pll ? ? up to six ccc blocks, one with an integrated pll ? configurable phase shift, multiply/divide, delay capabilities and external feedback ? wide input frequency range (1.5 mhz to 350 mhz) embedded memory ? 1 kbit of flashrom user nonvolatile memory ? srams and fifos with variable-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations) ? ? true dual-port sram (except 18 organization) ? enhanced commercial temperature range ? ?20c to +70c ? a3pn030 and smaller devices do not support this feature. table 1 ? proasic3 nano devices proasic3 nano devices a3pn010 a3pn015 1 a3pn020 a3pn060 a3pn125 a3pn250 proasic3 nano-z devices 1 a3pn030z 1,2 a3pn060z 1 a3pn125z 1 a3n250z 1 system gates 10,000 15,000 20,000 30,000 60,000 125,000 250,000 typical equivalent macrocells 86 128 172 256 512 1,024 2,048 versatiles (d-flip-flops) 260 384 520 768 1,536 3,072 6,144 ram kbits (1,024 bits) 2 ? ? ? ? 18 36 36 4,608-bit blocks 2 ??? ? 4 8 8 flashrom kbits 1 1 1 1 1 1 1 secure (aes) isp 2 ??? ? yesyesyes integrated pll in cccs 2 ??? ? 1 1 1 versanet globals 4 4 4 6 18 18 18 i/o banks 2 3 3 2 2 2 4 maximum user i/os (packaged device) 34 49 49 77 71 71 68 maximum user i/os (known good die) 34 ? 52 83 71 71 68 package pins qfn vqfp qn48 qn68 qn68 qn48, qn68 vq100 vq100 vq100 vq100 notes: 1. not recommended for new designs. 2. a3pn030z and smaller devices do not support this feature. 3. for higher densities and support of additional features, refer to the proasic3 and proasic3e datasheets. revision 11
ii revision 11 i/os per package proasic3 nano device status proasic3 nano devices a3pn010 a3pn015 1 a3pn020 a3pn060 a3pn125 a3pn250 proasic3 nano-z devices 1 a3pn030z 1 a3pn060z 1 a3pn125z 1 a3pn250z 1 known good die 34 ? 52 83 71 71 68 qn48 34 ? ? 34 ? ? ? qn68 ? 49 49 49 ? ? ? vq100 ? ? ?77717168 notes: 1. not recommended for new designs. 2. when considering migrating your design to a lower- or higher-density device, refer to the proasic3 fpga fabric user?s guide to ensure compliance with design and board migration requirements. 3. "g" indicates rohs-compliant packages. refer to "proasic3 nano ordering information" on page iii for the location of the "g" in the part number. for nano dev ices, the vq100 package is offered in both leaded and rohs-compliant versions. all other packages are rohs-compliant only. table 2 ? proasic3 nano fpgas package sizes dimensions packages qn48 qn68 vq100 length width (mm\mm) 6 x 6 8 x 8 14 x 14 nominal area (mm2) 36 64 196 pitch (mm) 0.4 0.4 0.5 height (mm) 0.90 0.90 1.20 proasic3 nano devices status proasic3 nano-z devices status a3pn010 production a3pn015 not recommended for new designs. a3pn020 production a3pn030z not recommended for new designs. a3pn060 production a3pn060z not recommended for new designs. a3pn125 production a3pn125z not recommended for new designs. a3pn250 production a3pn250z not recommended for new designs.
proasic3 nano flash fpgas revision 11 iii proasic3 nano ordering information devices not recommended for new designs a3pn015, a3pn030z, a3pn060z, a3pn125z, and a3pn250z are not recommended for new designs. device marking microsemi normally topside marks the full ordering part number on each device. there are some exceptions to this, such as some of the z feature grade nano devices, the v2 designator for igloo devices, and packages where space is physically limited. packages that have limited characters available ar e uc36, uc81, cs81, qn48, qn68, and qfn132 . on these specific packages, a subset of the device marking will be used that includes the required legal information and as much of the pa rt number as allowed by chara cter limitation of the device. in this case, devices will have a trunc ated device marking and may exclude the applications markings, such as the i designator for industrial devices or the es designator for engineering samples. figure 1 on page 1-iv shows an example of device marking based on the agl030v5-ucg81. note: *for the a3pn060, a3pn125, and a3pn250, the z feature gr ade does not support the enhanc ed nano features of schmitt trigger input, cold-sparing, and hot-swap i/o capability. the a3 pn030 z feature grade does not support schmitt trigger input. for the vq100, cs81, uc81, qn68, and qn48 packages, the z feature grade and the n part number are not marked on the device. a3pn010 = 10,000 system gates a3pn015 = 15,000 system gates (a3pn015 is not recommended for new designs) a3pn020 = 20,000 system gates a3pn030 = 30,000 system gates a3pn060 = 60,000 system gates a3pn125 = 125,000 system gates a3pn250 = 250,000 system gates speed grade blank = standard blank = standard feature grade z = nano devices without enhanced features* (not recommended for new designs) a 3pn250 z 1 vq _ part number proasic3 nano devices package type vq = very thin quad flat pack (0.5 mm pitch) dielot = known good die qn = quad flat pack no leads (0.4 mm and 0.5 mm pitches) 100 yi package lead count g lead-free packaging application (temperature range) blank = commercial (0c to +70c ambient temperature) i = industrial ( ? 40c to +85c ambient temperature) blank = standard packaging g= rohs-compliant packaging pp = pre-production es = engineering sample (room temperature only) 1 = 15% faster than standard 2 = 25% faster than standard security feature y = device includes license to implement ip based on the cryptography research, inc. (cri) patent portfolio blank = device does not include license to implement ip based on the cryptography research, inc. (cri) patent portfolio
iv revision 11 the actual mark will vary by the device/package combination ordered. proasic3 nano products available in the z feature grade temperature grade offerings speed grade and temperature grade matrix contact your local microsemi soc products gr oup representative for device availability: http://www.microsemi.com/soc/contact/default.aspx . figure 1 ? example of device marking fo r small form factor packages devices a3pn030* a3pn060* a3pn125* a3pn250* packages qn48 ? ? ? qn68 ? ? ? vq100 vq100 vq100 vq100 note: * not recommended for new designs. proasic3 nano devices a3pn010 a3pn015* a3pn020 a3pn060 a3pn125 a3pn250 proasic3 nano-z devices* a3pn030z* a3pn060z* a3pn125z* a3pn250z* qn48 c, i ? ? c, i ? ? ? qn68 ? c, i c, i c, i ? ? ? vq100 ? ? ? c, i c, i c, i c, i note: * not recommended for new designs. c = commercial temperature range: 0c to 70c ambient temperature i = industrial temperature range: ?40c to 85c ambient temperature temperature grade std. c 1 ? i 2 ? notes: 1. c = commercial temperature range: 0c to 70c ambient temperature. 2. i = industrial temperature range: ?40c to 85c ambient temperature. actelxxx agl030yww ucg81xxxx xxxxxxxx country of origin date code customer mark (if applicable) device name (six characters) package wafer lot #
proasic3 nano flash fpgas revision 11 v table of contents proasic3 nano device overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 proasic3 nano dc and sw itching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 versatile characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 clock conditioning circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 embedded sram and fifo characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 embedded flashrom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 jtag 1532 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71 pin descriptions and packaging supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 user pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 special function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 package pin assignments 48-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 68-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 100-pin vqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

revision 11 1-1 1 ? proasic3 nano device overview general description proasic3, the third-generation fami ly of microsemi flash fpgas, of fers performance, density, and features beyond thos e of the proasic plus ? family. nonvolatile flash technology gives proasic3 nano devices the advantage of being a secure, low power, single-chip solution that is instant on. proasic3 nano devices are reprogrammable and offer time-to-mark et benefits at an asic-level unit cost. these features enable desig ners to create high-de nsity systems using existing asic or fpga design flows and tools. proasic3 nano devices offer 1 kbit of on-chip, re programmable, nonvolatile flashrom storage as well as clock conditioning circuitry based on an integrated phase-locked loop (pll). a3pn030 and smaller devices do not have pll or ram support. proasic3 nano devices have up to 250,000 system gates, supported with up to 36 kbits of true dual-port sram and up to 71 user i/os. proasic3 nano devices increase the breadth of the pr oasic3 product line by adding new features and packages for greater customer value in high volume consumer, portable, and battery-backed markets. added features include smaller footprint packages designed with two-layer pcbs in mind, low power, hot-swap capability, and schmitt trigger for greater fl exibility in low-cost and power-sensitive applications. flash advantages reduced cost of ownership advantages to the designer extend beyond low unit cost, performance, and ease of use. unlike sram- based fpgas, flash-based proasic3 nano devices allow all functionality to be instant on; no external boot prom is required. on-boar d security mechanisms prevent access to all the programming information and enable secure remote updates of th e fpga logic. designers can perform secure remote in-system reprogramming to support future design iterations and field upgra des with confidence that valuable intellectual property (ip) cannot be compro mised or copied. secure isp can be performed using the industry-standard aes algorithm. the proasic3 nano device architecture mitigates the need for asic migration at higher user volumes. this make s the proasic3 nano device a cost-effective asic replacement solution, especially for applicatio ns in the consumer, networking/communications, computing, and avionics markets. with a variety of devices under $1, proasic3 nano fpgas enable cost-effective implementation of programmable logic and quick time to market. security nonvolatile, flash-based proasic3 nano devices do no t require a boot prom, so there is no vulnerable external bitstream that can be ea sily copied. proasic3 nano devices incorporate flashlock, which provides a unique combination of reprogrammabilit y and design security without external overhead, advantages that only an fpga with n onvolatile flash programming can offer. proasic3 nano devices utilize a 128 -bit flash-based lock and a separa te aes key to provide the highest level of protection in the fpga industry for progra mmed intellectual property and configuration data. in addition, all flashrom data in proasic3 nano de vices can be encrypted prior to loading, using the industry-leading aes-128 (fips192 ) bit block cipher encryption standard. the aes standard was adopted by the national institute of standards and technology (nist) in 2000 and replaces the 1977 des standard. proasic3 nano devices have a built-in aes decry ption engine and a flash-based aes key that make them the most co mprehensive programmable logic device security solution available today. proasic3 nano devices with aes-based security pr ovide a high level of protection for remote field updates over public networks such as the internet, and are designed to ensure that valuable ip remains out of the hands of system overbuilders, system cloners, and ip thieves.
proasic3 nano device overview 1-2 revision 11 security, built into the fpga fabric, is an inheren t component of proasic3 nano devices. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. proasic3 nano devices, with flashlock and aes security, are unique in being highly resistant to both invasive and noninvasive attacks. your valuable ip is protected with industry-standard security, making remote isp possible. a proasic3 nano device provides the best available securi ty for programmable logic designs. single chip flash-based fpgas store their configuration informati on in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga st ructure, and no external configuration data needs to be loaded at system power-up (unlike sram-based fpgas). therefore, flash-based proasic3 nano fpgas do not require system configuration compo nents such as eeproms or microcontrollers to load device configuration data. this reduces bill-of-materi als costs and pcb area, and increases security and system reliability. instant on microsemi flash-based proasic3 nano devices support level 0 of the instant on classification standard. this feature helps in system component initializ ation, execution of critic al tasks before the processor wakes up, setup and configuration of memory blo cks, clock generation, and bus activity management. the instant on f eature of flash-based proasic3 nano devices greatly simplifies total system design and reduces total system cost, often e liminating the need for cplds and cl ock generation plls that are used for these purposes in a system. in addition, glitch es and brownouts in system power will not corrupt the proasic3 nano device's flash configuration, and un like sram-based fpgas, the device will not have to be reloaded when system power is restored. this enab les the reduction or complete removal of the configuration prom, expensive voltage monitor, br ownout detection, and clock generator devices from the pcb design. flash-based proasic3 nano devices simplify total system design and reduce cost and design risk while increas ing system reliability and impr oving system init ialization time. firm errors firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prevent in sram fpgas. the consequence of this type of error can be a complete system failure. firm errors do not exist in the configuration memory of proasic3 nano flash- based fpgas. once it is programmed, the flash cell configuration element of proasic3 nano fpgas cannot be altered by high-energy ne utrons and is therefor e immune to them. recoverable (or soft) errors occur in the user data sram of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. low power flash-based proasic3 nano devices exhibit power ch aracteristics similar to an asic, making them an ideal choice for power-sensitive applications. proasi c3 nano devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many fpgas. proasic3 nano devices also have low dynamic powe r consumption to further maximize power savings. advanced flash technology proasic3 nano devices offer many benefits, includ ing nonvolatility and reprogrammability through an advanced flash-based, 130-nm lvcmos process with seven layers of metal. standard cmos design techniques are used to implement logic and contro l functions. the combination of fine granularity, enhanced flexible routing resources, and abundant fl ash switches allows for very high logic utilization without compromising device routability or perform ance. logic functions within the device are interconnected through a four-level routing hierarchy.
proasic3 nano flash fpgas revision 11 1-3 advanced architecture the proprietary proasic3 nano architecture provid es granularity comparable to standard-cell asics. the proasic3 nano device consists of five dist inct and programmable architectural features ( figure 1-3 to figure 1-4 on page 1-4 ): ? fpga versatiles ? dedicated flashrom ? dedicated sram/fifo memory ? extensive cccs and plls ? advanced i/o structure note: *bank 0 for the a3pn030 device figure 1-1 ? proasic3 device architecture overvi ew with two i/o banks and no ram (a3pn010 and a3pn030) figure 1-2 ? proasic3 nano architecture overview with three i/o banks and no ram (a3pn015 and a3pn020) versatile i/os user nonvolatile flashrom charge pumps bank 1* bank 1 bank 0 bank 1 ccc-gl versatile i/os user nonvolatile flashrom charge pumps bank 1 bank 2 bank 0 bank 1 ccc-gl
proasic3 nano device overview 1-4 revision 11 the fpga core consists of a sea of versatiles. each versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by progr amming the appropriate flash switch interconnections. the versatility of the proasic3 nano co re tile as either a three-input lookup table (lut) equivalent or as a d-flip-flop/latch with enable allows for efficient use of the fpga fabric. the versatile capability is unique to the proasic3 family of thir d-generation architecture flash fpgas. versatiles are connected with any of the four leve ls of routing hierarchy. flash swit ches are distributed throughout the device to provide nonvolatile, reconfigurable inte rconnect programming. maximum core utilization is possible for virtually any design. figure 1-3 ? proasic3 nano device architecture overview with two i/o banks (a3pn060 and a3pn125) figure 1-4 ? proasic3 nano device architecture overview with four i/o banks (a3pn250) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2
proasic3 nano flash fpgas revision 11 1-5 versatiles the proasic3 nano core consists of versatile s, which have been enhan ced beyond the proasic plus ? core tiles. the proasic3 nano versatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set refer to figure 1-5 for versatile configurations. user nonvolatile flashrom proasic3 nano devices have 1 kbit of on-chip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business models (for example, set-top boxes) ? secure key storage for secure communications algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using the standard proa sic3 nano ieee 1532 jtag programming interface. the core can be individually programmed (erased and written), and on-chip aes decryption can be used selectively to securely load data over public networ ks (except in the a3pn030 and smaller devices), as in security keys stored in the fl ashrom for a user design. the flashrom can be programmed via the jtag progr amming interface, and its contents can be read back either through the jtag programming interface or via direct fpga core addressing. note that the flashrom can only be programmed from the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bits ; however, reading is performed on a byte-by-byte basis using a synchronous interface. a 7-bit address fr om the fpga core defines which of the 8 banks and which of the 16 bytes within that bank are being read. the three most significant bits (msbs) of the flashrom address determine the bank, and the four least significant bits (lsbs) of the flashrom address define the byte. the proasic3 nano development software solutions, libero ? system-on-chip (soc) software and designer, have extensive support for the flashrom. one such feature is aut o-generation of sequential programming files for applications requiring a unique serial number in each part. another feature enables the inclusion of static data for system version co ntrol. data for the flashrom can be generated quickly and easily using libero soc and designer software to ols. comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing flashrom contents. figure 1-5 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
proasic3 nano device overview 1-6 revision 11 sram and fifo proasic3 nano devices (except th e a3pn030 and smaller devices) have embedded sram blocks along their north and south sides. each variable-aspect-rati o sram block is 4,608 bits in size. available memory configurations ar e 25618, 5129, 1k4, 2k2, and 4k1 bits. the in dividual blocks have independent read and write ports that can be confi gured with different bit widths on each port. for example, data can be sent through a 4-bit port and read as a single bitstream. the embedded sram blocks can be initialized via the device jtag port (rom emulation mode) using the ujtag macro (except in a3pn030 and smaller devices). in addition, every sram block has an embedded fi fo control unit. the contro l unit allows the sram block to be configured as a synchronous fifo with out using additional core versatiles. the fifo width and depth are programmable. the fifo also feat ures programmable almost empty (aempty) and almost full (afull) flags in addition to the norma l empty and full flags. the embedded fifo control unit contains the counters necessary for generati on of the read and write address pointers. the embedded sram/fifo blocks can be cascaded to create larger configurations. pll and ccc higher density proasic3 nano devices using either the two i/o bank or four i/o bank architectures provide the designer with very flexible clock co nditioning capabilities. a3pn060, a3pn125, and a3pn250 contain six cccs. one ccc (center west side) has a pll. the a3pn030 and smaller devices use different cccs in their arch itecture. these ccc-gls contain a global mux but do not have any plls or programmable delays. for devices using the six ccc block architecture, these six ccc blocks are located at the four corners and the centers of the east and west sides. all six ccc blocks are usable; the four corner cccs and the east ccc allo w simple clock delay operations as well as clock spine access. the inpu ts of the six ccc blocks are accessible from the fpga core or from dedicated connections to the ccc block, which are located near the ccc. the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz to 350 mhz ? output frequency range (f out_ccc ) = 0.75 mhz to 350 mhz ? clock delay adjustment via programmable a nd fixed delays from ?7.56 ns to +11.12 ns ? 2 programmable delay types for clock skew minimization ? clock frequency synthesis (for pll only) additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270. output phase shift depends on the output divider configuration (for pll only). ? output duty cycle = 50% 1.5% or better (for pll only) ? low output jitter: worst case < 2.5% clock per iod peak-to-peak period jitter when single global network used (for pll only) ? maximum acquisition time = 300 s (for pll only) ? low power consumption of 5 mw ? exceptional tolerance to input period jitter?allowabl e input jitter is up to 1.5 ns (for pll only) ? four precise phases; maximum misalignment between adjacent phases of 40 ps (350 mhz / f out_ccc ) (for pll only) global clocking proasic3 nano devices have extensive support for mu ltiple clocking domains. in addition to the ccc and pll support described above, there is a co mprehensive global clock distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the versanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets.
proasic3 nano flash fpgas revision 11 1-7 i/os with advanced i/o standards proasic3 nano fpgas feature a flexible i/o structure, supporting a range of voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v). the i/os are organized into banks, with two, three, or four banks per device. t he configuration of these banks determines the i/o standards supported. each i/o module contains several input, output, and enable registers. these registers allow the implementation of various single-data-rate applicatio ns for all versions of nano devices and double-data- rate applications for the a3pn060, a3pn125, and a3pn250 devices. proasic3 nano devices support lvttl and lvcmos i/o standards, are hot-swappable, and support cold-sparing and schmitt trigger. hot-swap (also called hot-plug, or hot-insertion) is t he operation of hot-insertion or hot-removal of a card in a powered-up system. cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. wide range i/o support proasic3 nano devices support jedec-defined wide r ange i/o operation. proasic3 nano supports the jesd8-b specification, covering both 3 v and 3.3 v supplies, for an effective operating range of 2.7 v to 3.6 v. wider i/o range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components wit h greater tolerances. wide range eases i/o bank management and provides enhanc ed protection from system voltage sp ikes, while providing the flexibility to easily run custom voltage applications. specifying i/o states during programming you can modify the i/o states during programming in fl ashpro. in flashpro, this feature is supported for pdb files generated from designer v8.5 or greater. see the flashpro user?s guide for more information. note: pdb files generated from designer v8.1 to designer v8.4 (including all service packs) have limited display of pin numbers only. 1. load a pdb from the flashpro gui. you must have a pdb loaded to modify the i/o states during programming. 2. from the flashpro gui, click pdb configurat ion. a flashpoint ? pr ogramming file generator window appears. 3. click the specify i/o states during programming button to display the specify i/o states during programming dialog box. 4. sort the pins as desired by clicking any of the column headers to sort the entries by that header. select the i/os you wish to modify ( figure 1-6 on page 1-8 ). 5. set the i/o output state. you can set basic i/o se ttings if you want to use the default i/o settings for your pins, or use custom i/o settings to cust omize the settings for each pin. basic i/o state settings: 1 ? i/o is set to drive out logic high 0 ? i/o is set to drive out logic low last known state ? i/o is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming
proasic3 nano device overview 1-8 revision 11 z -tri-state: i/o is tristated 6. click ok to return to the flashpoint ? programming file generator window. i/o states during programming are saved to the ad b and resulting programming files after completing programming file generation. figure 1-6 ? i/o states during programming window
revision 11 2-1 2 ? proasic3 nano dc and switching characteristics general specifications the z feature grade does not support the enhanced na no features of schmitt tr igger input, cold-sparing, and hot-swap i/o capability. refer to the "proasic3 nano ordering information" section on page iii for more information. dc and switching characteristics for ?f speed grade targets are based only on simulation. the characteristics provided for the ?f speed grade are subject to change after establishing fpga specifications. some restrictions might be added and will be reflected in future revisions of this document. the ?f speed grade is only suppo rted in the commercial temperature range. operating conditions stresses beyond those listed in ta b l e 2 - 1 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of th e device at these or any other conditions beyond those listed under the recommended o perating conditions specified in table 2-2 on page 2-2 is not implied. table 2-1 ? absolute maximum ratings symbol parameter limits units vcc dc core supply voltage ?0.3 to 1.65 v vjtag jtag dc voltage ?0.3 to 3.75 v vpump programming voltage ?0.3 to 3.75 v vccpll analog power supply (pll) ?0.3 to 1.65 v vcci dc i/o output buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v v t stg 1 storage temperature ?65 to +150 c t j 1 junction temperature +125 c notes: 1. for flash programming and retention maximum limits, refer to table 2-3 on page 2-2 , and for recommended operating limits, refer to table 2-2 on page 2-2 . 2. vmv pins must be connected to the corresponding vcci pins. see the "vmvx i/o supply voltage (quiet)" section on page 3-1 for further information. 3. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undershoot or overshoot according to the limits shown in table 2-4 on page 2-3 .
proasic3 nano dc and switching characteristics 2-2 revision 11 table 2-2 ? recommended operating conditions 1, 2 symbol parameter extended commercial industrial units t a ambient temperature ?20 to +70 2 ?40 to +85 2 c t j junction temperature ?20 to +85 ?40 to +100 c vcc 3 1.5 v dc core supply voltage 1.425 to 1.575 1.425 to 1.575 v vjtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v vpump 4 programming voltage programming mode 4 3.15 to 3.45 3.15 to 3.45 v operation 5 0 to 3.6 0 to 3.6 v vccpll 6 analog power supply (pll) 1.5 v dc core supply voltage 3 1.425 to 1.575 1.425 to 1.575 v vcci and vmv 7 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v 3.3 v wide range supply voltage 8 2.7 to 3.6 2.7 to 3.6 v notes: 1. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 2. to ensure targeted reliability standards are met across ambient and junction operating temperatures, microsemi recommends that the user follow best design practices using microsemi?s timing and power simulation tools. 3. the ranges given here are for power supplies only. t he recommended input voltage ranges specific to each i/o standard are given in table 2-14 on page 2-16 . vmv and vcci should be at the same voltage within a given i/o bank. 4. the programming temperature range su pported is tambient = 0c to 85c. 5. vpump can be left floating during operation (not programming mode). 6. vccpll pins should be tied to vcc pins. see the "pin descriptions and packaging" chapter for further information. 7. vmv pins must be connected to the corresponding vcci pins. see the "pin descriptions and packaging" chapter for further information. 8. 3.3 v wide range is compliant to the jesd8-b specification and supports 3.0 v vcci operation. table 2-3 ? flash programming limits ? retention, storage and operating temperature 1 product grade programming cycles program retention (biased/unbiased) maximum storage temperature t stg (c) 2 maximum operating junction temperature t j (c) 2 commercial 500 20 years 110 100 industrial 500 20 years 110 100 notes: 1. this is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. these limits apply for program/data retention only. refer to table 2-1 on page 2-1 and table 2-2 for device operating conditions and absolute limits.
proasic3 nano flash fpgas revision 11 2-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circui try is designed into every proasic ? 3 device. these circuits ensure easy transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any sequence with mi nimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-1 on page 2-4 . there are five regions to consider during power-up. proasic3 i/os are activated only if all of the following three conditions are met: 1. vcc and vcci are above the minimum specified trip points ( figure 2-1 on page 2-4 ). 2. vcci > vcc ? 0.75 v (typical) 3. chip is in the operating mode. vcci trip point: ramping up: 0.6 v < trip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v vcc trip point: ramping up: 0.6 v < trip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v vcc and vcci ramp-up trip points are about 100 mv hi gher than ramp-down trip points. this specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tristated and weakly pulled up to vcci. ? jtag supply, pll power supplies, and charge pump vpump supply have no influence on i/o behavior. pll behavior at brownout condition microsemi recommends using monotonic power supplie s or voltage regulators to ensure proper power- up behavior. power ramp-up should be monotonic at least until vcc and vccpllx exceed brownout activation levels. the vcc activation level is specified as 1.1 v worst-case (see figure 2-1 on page 2-4 for more details). when pll power supply voltage and/or vcc levels drop below the vcc brownout levels (0.75 v 0.25 v), the pll output lock signal goes low and/ or the output clock is lost. refer to the "power-up/-down behavior of low po wer flash devices" chapter of the proasic3 nano fpga fabric user?s guide for information on clock and lock recovery. table 2-4 ? overshoot and undershoot limits 1 vcci and vmv average vcci?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one out of si x clock cycles. if the overshoot/unders hoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 v.
proasic3 nano dc and switching characteristics 2-4 revision 11 internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns delay from input buffer activation figure 2-1 ? i/o state as a function of vcci and vcc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional but slower because vcci / vcc are below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh / vol levels. min vcci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v vcc vcc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v d eactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v vcc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, vih / vil , voh / vol , etc. region 4: i/o buffers are on. i/os are functional but slower because vcci is below specification. for the same reason, input buffers do not meet vih / vil levels, and output buffers do not meet voh/vol levels. where vt can be from 0.58 v to 0.9 v (typically 0.75 v) vcci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the vcc is below specification. vcc = vcci + vt
proasic3 nano flash fpgas revision 11 2-5 thermal characteristics introduction the temperature variable in the designer software re fers to the junction temperature, not the ambient temperature. this is an importan t distinction because dynamic and st atic power consumption cause the chip junction to be higher than the ambient temperature. eq 1 can be used to calculate junction temperature. t j = junction temperature = ? t + t a eq 1 where: t a = ambient temperature ? t = temperature gradient between junction (silicon) and ambient ? t = ? ja * p ? ja = junction-to-ambient of the package. ? ja numbers are located in table 2-5 . p = power dissipation package thermal characteristics the device junction-to-case thermal resistivity is ? jc and the junction-to-ambient air thermal resistivity is ? ja . the thermal characteristics for ? ja are shown for two air flow rates. the absolute maximum junction temperature is 100c. eq 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin fbga package at commercial temperature and in still air. eq 2 temperature and voltage derating factors maximum power allowed max. junction temp. ( ? c) max. ambient temp. ( ? c) ? ? ja ( ? c/w) ------------------------------------------------------------------------------------------------------------------------------- ----------- 100 ? c70 ? c ? 20.5 ? c/w ------------------------------------- 1.463 w = = = table 2-5 ? package thermal resistivities package type device pin count ? jc ? ja units still air 200 ft./min. 500 ft./min. quad flat no lead (qfn) all devices 48 tbd tbd tbd tbd c/w 68 tbd tbd tbd tbd c/w 100 tbd tbd tbd tbd c/w very thin quad flat pack (vqfp) all devices 100 10.0 35.3 29.4 27.1 c/w table 2-6 ? temperature and voltage derati ng factors for timing delays (normalized to t j = 70c, vcc = 1.425 v) array voltage vcc (v) junction temperature (c) ?40c ?20c 0c 25c 70c 85c 100c 1.425 0.968 0.973 0.979 0.991 1.000 1.006 1.013 1.500 0.888 0.894 0.899 0.910 0.919 0.924 0.930 1.575 0.836 0.841 0.845 0.856 0.864 0.870 0.875
proasic3 nano dc and switching characteristics 2-6 revision 11 calculating power dissipation quiescent supply current power per i/o pin table 2-7 ? quiescent supply current characteristics a3pn010 a3pn015 a3pn020 a3pn060 a3pn125 a3pn250 typical (25c) 600 a 1 ma 1 ma 2 ma 2 ma 3 ma max. (commercial) 5 ma 5 ma 5 ma 10 ma 10 ma 20 ma max. (industrial) 8 ma 8 ma 8 ma 15 ma 15 ma 30 ma note: idd includes vcc, vpump, and vcci, currents. table 2-8 ? summary of i/o input buffe r power (per pin) ? defa ult i/o software settings vcci (v) dynamic power, pac9 (w/mhz) 1 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 16.45 3.3 v lvttl / 3.3 v lvcmos ? schmitt trigger 3.3 18.93 3.3 v lvcmos wide range 2 3.3 16.45 3.3 v lvcmos wide range ? schmitt trigger 3.3 18.93 2.5 v lvcmos 2.5 4.73 2.5 v lvcmos ? schmitt trigger 2.5 6.14 1.8 v lvcmos 1.8 1.68 1.8 v lvcmos ? schmitt trigger 1.8 1.80 1.5 v lvcmos (jesd8-11) 1.5 0.99 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 0.96 notes: 1. pac9 is the total dynamic power measured on vcci. 2. all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range as specified in the jesd8-b specification.
proasic3 nano flash fpgas revision 11 2-7 table 2-9 ? summary of i/o output bu ffer power (per pin) ? de fault i/o softw are settings 1 c load (pf) 2 vcci (v) dynamic power, pac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 10 3.3 162.01 3.3 v lvcmos wide range 4 10 3.3 162.01 2.5 v lvcmos 10 2.5 91.96 1.8 v lvcmos 10 1.8 46.95 1.5 v lvcmos (jesd8-11) 10 1.5 32.22 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. values for a3pn020, a3pn015, and a3pn010. a3pn060, a3pn125, and a3pn250 correspond to a default loading of 35 pf. 3. pac10 is the total dynamic power measured on vcci. 4. all lvcmos3.3 v software macros support lvcmos 3.3 v wide range as specified in the jesd8-b specification.
proasic3 nano dc and switching characteristics 2-8 revision 11 power consumption of vari ous internal resources table 2-10 ? different components contributing to dynamic power consumption in proasic3 nano devices parameter definition device specific dynamic contributions (w/mhz) a3pn250 a3pn125 a3pn060 a3pn020 a3pn015 a3pn010 pac1 clock contribution of a global rib 11.03 11.03 9.3 9.3 9.3 9.3 pac2 clock contribution of a global spine 1.58 0.81 0.81 0.4 0.4 0.4 pac3 clock contribution of a versatile row 0.81 pac4 clock contribution of a versatile used as a sequential module 0.12 pac5 first contribution of a versatile used as a sequential module 0.07 pac6 second contribution of a versatile used as a sequential module 0.29 pac7 contribution of a versatile used as a combinatorial module 0.29 pac8 average contribution of a routing net 0.70 pac9 contribution of an i/o input pin (standard-dependent) see table 2-8 on page 2-6 . pac10 contribution of an i/o output pin (standard-dependent) see table 2-9 on page 2-7 . pac11 average contribution of a ram block during a read operation 25.00 n/a pac12 average contribution of a ram block during a write operation 30.00 n/a pac13 dynamic contribution for pll 2.60 n/a note: for a different output load, drive strength, or slew rate, microsemi recommends using the microsemi power spreadsheet calculator or smar tpower tool in libero soc. table 2-11 ? different components contributing to the static power consumption in proasic3 nano devices parameter definition device specific static power (mw) a3pn250 a3pn125 a3pn060 a3pn020 a3pn015 a3pn010 pdc1 array static power in active mode see table 2-7 on page 2-6 . pdc4 static pll contribution 1 2.55 n/a pdc5 bank quiescent power (vcci-dependent) see table 2-7 on page 2-6 . notes: 1. minimum contribution of the pll when running at lowest frequency. 2. for a different output load, drive strength, or slew rate, microsemi recommends using the microsemi power spreadsheet calculator or smartpower tool in libero soc.
proasic3 nano flash fpgas revision 11 2-9 power calculation methodology this section describes a simplified method to estima te power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in libero soc. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number a nd the frequency of each output clock generated ? the number of combinatorial and sequential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-12 on page 2-11 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-13 on page 2-11 . ? read rate and write rate to the memory?guidel ines are provided for typical applications in table 2-13 on page 2-11 . the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = pdc1 + n inputs * pdc2 + n outputs * pdc3 n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (pac1 + n spine *pac2 + n row *pac3 + n s-cell * pac4) * f clk n spine is the number of global spines used in the user design?guidelines are provided in the " spine architecture" section of the global resources chapter in the proasic3 nano fpga fabric user's guide . n row is the number of versatile rows used in the design?guidelines are provided in the " spine architecture" section of the global resources chapter in the proasic3 nano fpga fabric user's guide . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. pac1, pac2, pac3, and pac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (pac5 + ? 1 / 2 * pac6) * f clk n s-cell is the number of versatiles used as sequent ial modules in the design. when a multi-tile sequential cell is used, it should be accounted for as 1. ? 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency.
proasic3 nano dc and switching characteristics 2-10 revision 11 combinatorial cells contribution?p c-cell p c-cell = n c-cell * ? 1 / 2 * pac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. ? 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * ? 1 / 2 * pac8 * f clk n s-cell is the number of versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. ? 1 is the toggle rate of versatile ou tputs?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * ? 2 / 2 * pac9 * f clk n inputs is the number of i/o input buffers used in the design. ? 2 is the i/o buffer toggle rate?guidelines are provided in table 2-12 on page 2-11 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * ? 2 / 2 * ? 1 * pac10 * f clk n outputs is the number of i/o output buffers used in the design. ? 2 is the i/o buffer toggle rate?guidelines are provided in table 2-12 on page 2-11 . ? 1 is the i/o buffer enable rate?guidelines are provided in table 2-13 on page 2-11 . f clk is the global clock signal frequency. ram contribution?p memory p memory = pac11 * n blocks * f read-clock * ? 2 + pac12 * n block * f write-clock * ? 3 n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. ? 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. ? 3 is the ram enable rate for write operations?guidelines are provided in table 2-13 on page 2-11 . pll contribution?p pll p pll = pdc4 + pac13 * f clkout f clkout is the output clock frequency. 1 1. the pll dynamic contribution depends on th e input clock frequency, the number of output clock signals generated by the pll, and the frequency of each output clock. if a pll is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (p ac14 * f clkout product) to the total pll contribution.
proasic3 nano flash fpgas revision 11 2-11 guidelines toggle rate definition a toggle rate defines the frequency of a net or logic elem ent relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 enable rate definition output enable rate is the average percentage of ti me during which tristate outputs are enabled. when nontristate output buffers are used, the enable rate should be 100%. table 2-12 ? toggle rate guidelines reco mmended for power calculation component definition guideline ? 1 toggle rate of versatile outputs 10% ? 2 i/o buffer toggle rate 10% table 2-13 ? enable rate guidelines recomme nded for power calculation component definition guideline ? 1 i/o output buffer enable rate 100% ? 2 ram enable rate for read operations 12.5% ? 3 ram enable rate for write operations 12.5%
proasic3 nano dc and switching characteristics 2-12 revision 11 user i/o characteristics timing model figure 2-2 ? timing model operating conditions: ?2 speed, commercial temperature range (t j = 70c), worst case vcc = 1.425 v, with default loading at 10 pf dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvcmos 2.5v output drive strength = 8 ma high slew rate input lvcmos 2.5 v lvcmos 1.5 v lvttl 3.3 v output drive strength = 8 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 2 ma high slew rate lvttl output drive strength = 4 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 0.56 ns t pd = 0.49 ns t dp = 2.25 ns t pd = 0.87 ns t dp = 2.87 ns t pd = 0.51 ns t dp = 2.21 ns t pd = 0.47 ns t dp = 3.02 ns t pd = 0.47 ns t py = 0.84 ns t clkq = 0.55 ns t oclkq = 0.59 ns t sud = 0.43 ns t osud = 0.31 ns t dp = 2.21 ns t py = 0.84 ns t py = 1.14 ns t clkq = 0.55 ns t sud = 0.43 ns t py = 0.84 ns t iclkq = 0.24 ns t isud = 0.26 ns t py = 1.04 ns
proasic3 nano flash fpgas revision 11 2-13 figure 2-3 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50% 50% vih vcc vil t din (r) din gnd t din (f) 50% 50% vcc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
proasic3 nano dc and switching characteristics 2-14 revision 11 figure 2-4 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) vtrip vtrip voh vcc d 50% 50% vcc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
proasic3 nano flash fpgas revision 11 2-15 figure 2-5 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% v cci t zl vtrip 50% t hz 90% vcci t zh vtrip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls vtrip 50% t zhs vtrip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% vcc vcc vcc vcci vcc vcc vcc voh vol vol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
proasic3 nano dc and switching characteristics 2-16 revision 11 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-14 ? summary of maximum and minimu m dc input and output levels applicable to commercial and industrial conditions?softwar e default settings i/o standard drive strength equivalent software default drive strength option 2 slew rate vil vih vol voh iol 1 ioh 1 min. v max v min. v max. v max. v min. vmama 3.3 v lvttl/ 3.3 v lvcmos 8 ma 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 3.3 v lvcmos wide range 100 a 8 ma high ?0.3 0.8 2 3.6 0.2 vcci ? 0.2 100 a 100 a 2.5 v lvcmos 8 ma 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma 4 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 1.5 v lvcmos 2 ma 2 ma high ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 notes: 1. currents are measured at 85c junction temperature. 2. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models . 3. all lvcmos 3.3 v software macros suppo rt lvcmos 3.3 v wide range, as specified in the jesd8-b specification. table 2-15 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions dc i/o standards commercial 1 industrial 2 iil 3 iih 4 iil 3 iih 4 a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 3.3 v lvcmos wide range 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 notes: 1. commercial range (?20c < t a < 70c) 2. industrial range (?40c < t a < 85c) 3. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 4. iih is the input leakage current per i/o pin over reco mmended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges.
proasic3 nano flash fpgas revision 11 2-17 summary of i/o timing characteristics ? default i/o software settings table 2-16 ? summary of ac measuring points standard measuring trip point (vtrip) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 3.3 v lvcmos wide range 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v table 2-17 ? i/o ac parameter definitions parameter parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer t dout data to output buffer delay through the i/o interface t eout enable to output buffer tristate co ntrol delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low
proasic3 nano dc and switching characteristics 2-18 revision 11 table 2-18 ? summary of i/o timing characteristics ?software default settings (at 35 pf) std speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.425 v for a3pn060, a3pn125, and a3pn250 i/o standard drive strength (ma) equivalent software default drive strength option 1 slew rate capacitive load (pf) t dout (ns) t dp (ns) t din (ns) t py (ns) t pys (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) 3.3 v lvttl / 3.3 v lvcmos 8 8 ma high 35 0.60 4.57 0.04 1.13 1 .52 0.43 4.64 3.92 2.60 3.14 3.3 v lvcmos wide range 100 a 8 ma high 35 0.60 6.78 0.04 1.5 7 2.18 0.43 6.78 5.72 3.72 4.35 2.5 v lvcmos 8 8 ma high 35 0.60 4.94 0.0 4 1.43 1.63 0.43 4.71 4.94 2.60 2.98 1.8 v lvcmos 4 4 ma high 35 0.60 6.53 0.0 4 1.35 1.90 0.43 5.53 6.53 2.62 2.89 1.5 v lvcmos 2 2 ma high 35 0.60 7.86 0.0 4 1.56 2.14 0.43 6.45 7.86 2.66 2.83 notes: 1. the minimum drive strength for any lvcmos 3.3 v softwa re configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros suppo rt lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-19 ? summary of i/o timing characteristics ?software default settings (at 10 pf) std speed grade, commercial-case conditions: t j = 70c, worst case vcc = 1.425 v for a3pn020, a3pn015, and a3pn010 i/o standard drive strength (ma) equivalent software default drive strength option 1 slew rate capacitive load (pf) t dout (ns) t dp (ns) t din (ns) t py (ns) t pys (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) 3.3 v lvttl / 3.3 v lvcmos 8 8 ma high 10 0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14 3.3 v lvcmos wide range 100a8ma high 10 0.603.940.041.572.180.433.943.163.724.35 2.5 v lvcmos 8 8 ma high 10 0.60 2.76 0. 04 1.43 1.63 0.43 2.80 2.60 2.60 2.98 1.8 v lvcmos 4 4 ma high 10 0.60 3.22 0. 04 1.35 1.90 0.43 3.24 3.22 2.62 2.89 1.5 v lvcmos 2 2 ma high 10 0.60 3.76 0. 04 1.56 2.14 0.43 3.74 3.76 2.66 2.83 notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. all lvcmos 3.3 v software macros suppo rt lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-19 detailed i/o dc characteristics table 2-20 ? input capacitance symbol definition cond itions min. max. units c in input capacitance vin = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin vin = 0, f = 1.0 mhz 8 pf table 2-21 ? i/o output buffer maximum resistances 1 standard drive strength r pull-down ( ? ) 2 r pull-up ( ? ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 3.3 v lvcmos wide range 100 a same as equivalent software default drive 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 1.5 v lvcmos 2 ma 200 224 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on vcci, drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models, located at http://www.microsemi.com/soc/download/ibis/default.aspx . 2. r (pull-down-max) = (volspec) / iolspec 3. r (pull-up-max) = (vccimax ? vohspec) / iohspec table 2-22 ? i/o weak pull-up/pull-down resistances minimum and maximum weak pull-u p/pull-down resistance values vcci r (weak pull-up) 1 ( ? ) r (weak pull-down) 2 ( ? ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 3.3 v (wide range i/os) 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-up-max) = (vccimax ? vohspec) / i (weak pull-up-min) 2. r (weak pulldown-max) = (volspec) / i (weak pulldown-min)
proasic3 nano dc and switching characteristics 2-20 revision 11 the length of time an i/o can withstand iosh/iosl events depends on the junc tion temperature. the reliability data below is based on a 3.3 v, 8 ma i/o setting, which is the worst case for this type of analysis. for example, at 100c, the short current condition would have to be sustained for more than six months to cause a reliability concern. the i/o design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-23 ? i/o short currents iosh/iosl drive strength iosl (ma)* iosh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 3.3 v lvcmos wide range 100 a same as equivalent software default drive 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 1.5 v lvcmos 2 ma 13 16 note: *t j = 100c table 2-24 ? duration of short circ uit event before failure temperature time before failure ?40c > 20 years ?20c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months
proasic3 nano flash fpgas revision 11 2-21 table 2-25 ? schmitt trigger input hysteresis hysteresis voltage value (typ.) for schmitt mode input buffers input buffer configuration hysteresis value (typ.) 3.3 v lvttl / lvcmos (schmitt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmitt trigger mode) 80 mv 1.5 v lvcmos (schmitt trigger mode) 60 mv table 2-26 ? i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/f all time (max.) reliability lvttl/lvcmos (schmitt trigger disabled) no requirement 10 ns * 20 years (100c) lvttl/lvcmos (schmitt trigger enabled) no requirement no requirement, but input noise voltage cannot exceed schmitt hysteresis 20 years (100c) note: the maximum input rise/fall time is related to the noise induced into the input buffer trace. if the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. microsemi recommends signal integrit y evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
proasic3 nano dc and switching characteristics 2-22 revision 11 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 2-27 ? minimum and maximum dc input and output levels 3.3 v lvttl / 3.3 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-6 ? ac loading table 2-28 ? 3.3 v lvttl/lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.410 notes: 1. measuring point = vtrip. see table 2-16 on page 2-17 for a complete table of trip points. 2. capacitive load for a3pn060, a3pn125, and a3pn250 is 35 pf. test point test point enable path datapath 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 35 pf for t hz / t lz
proasic3 nano flash fpgas revision 11 2-23 timing characteristics table 2-29 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 9.70 0.04 1.13 1. 52 0.43 9.88 8.82 2.31 2.50 ns ?1 0.51 8.26 0.04 0.96 1.29 0.36 8.40 7.50 1.96 2.13 ns ?2 0.45 7.25 0.03 0.84 1.13 0.32 7.37 6.59 1.72 1.87 ns 4 ma std. 0.60 9.70 0.04 1.13 1. 52 0.43 9.88 8.82 2.31 2.50 ns ?1 0.51 8.26 0.04 0.96 1.29 0.36 8.40 7.50 1.96 2.13 ns ?2 0.45 7.25 0.03 0.84 1.13 0.32 7.37 6.59 1.72 1.87 ns 6 ma std. 0.60 6.90 0.04 1.13 1. 52 0.43 7.01 6.22 2.61 3.01 ns ?1 0.51 5.87 0.04 0.96 1.29 0.36 5.97 5.29 2.22 2.56 ns ?2 0.45 5.15 0.03 0.84 1.13 0.32 5.24 4.64 1.95 2.25 ns 8 ma std. 0.60 6.90 0.04 1.13 1. 52 0.43 7.01 6.22 2.61 3.01 ns ?1 0.51 5.87 0.04 0.96 1.29 0.36 5.97 5.29 2.22 2.56 ns ?2 0.45 5.15 0.03 0.84 1.13 0.32 5.24 4.64 1.95 2.25 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-30 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 7.19 0.04 1.13 1. 52 0.43 7.32 6.40 2.30 2.62 ns ?1 0.51 6.12 0.04 0.96 1.29 0.36 6.22 5.44 1.96 2.23 ns ?2 0.45 5.37 0.03 0.84 1.13 0.32 5.46 4.78 1.72 1.96 ns 4 ma std. 0.60 7.19 0.04 1.13 1. 52 0.43 7.32 6.40 2.30 2.62 ns ?1 0.51 6.12 0.04 0.96 1.29 0.36 6.22 5.44 1.96 2.23 ns ?2 0.45 5.37 0.03 0.84 1.13 0.32 5.46 4.78 1.72 1.96 ns 6 ma std. 0.60 4.57 0.04 1.13 1. 52 0.43 4.64 3.92 2.60 3.14 ns ?1 0.51 3.89 0.04 0.96 1.29 0.36 3.95 3.33 2.22 2.67 ns ?2 0.45 3.41 0.03 0.84 1.13 0.32 3.47 2.93 1.95 2.34 ns 8 ma std. 0.60 4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14 ns ?1 0.51 3.89 0.04 0.96 1.29 0.36 3.95 3.33 2.22 2.67 ns ?2 0.45 3.41 0.03 0.84 1.13 0.32 3.47 2.93 1.95 2.34 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-24 revision 11 table 2-31 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 5.48 0.04 1.13 1. 52 0.43 5.58 5.21 2.31 2.50 ns ?1 0.51 4.66 0.04 0.96 1.29 0.36 4.74 4.43 1.96 2.13 ns ?2 0.45 4.09 0.03 0.84 1.13 0.32 4.16 3.89 1.72 1.87 ns 4 ma std. 0.60 5.48 0.04 1.13 1. 52 0.43 5.58 5.21 2.31 2.50 ns ?1 0.51 4.66 0.04 0.96 1.29 0.36 4.74 4.43 1.96 2.13 ns ?2 0.45 4.09 0.03 0.84 1.13 0.32 4.16 3.89 1.72 1.87 ns 6 ma std. 0.60 4.33 0.04 1.13 1. 52 0.43 4.40 4.14 2.61 3.01 ns ?1 0.51 3.69 0.04 0.96 1.29 0.36 3.75 3.52 2.22 2.56 ns ?2 0.45 3.24 0.03 0.84 1.13 0.32 3.29 3.09 1.95 2.25 ns 8 ma std. 0.60 4.33 0.04 1.13 1. 52 0.43 4.40 4.14 2.61 3.01 ns ?1 0.51 3.69 0.04 0.96 1.29 0.36 3.75 3.52 2.22 2.56 ns ?2 0.45 3.24 0.03 0.84 1.13 0.32 3.29 3.09 1.95 2.25 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-32 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 3.56 0.04 1.13 1. 52 0.43 3.62 3.03 2.30 2.62 ns ?1 0.51 3.03 0.04 0.96 1.29 0.36 3.08 2.58 1.96 2.23 ns ?2 0.45 2.66 0.03 0.84 1.13 0.32 2.70 2.26 1.72 1.96 ns 4 ma std. 0.60 3.56 0.04 1.13 1. 52 0.43 3.62 3.03 2.30 2.62 ns ?1 0.51 3.03 0.04 0.96 1.29 0.36 3.08 2.58 1.96 2.23 ns ?2 0.45 2.66 0.03 0.84 1.13 0.32 2.70 2.26 1.72 1.96 ns 6 ma std. 0.60 2.73 0.04 1.13 1. 52 0.43 2.77 2.23 2.60 3.14 ns ?1 0.51 2.32 0.04 0.96 1.29 0.36 2.36 1.90 2.22 2.67 ns ?2 0.45 2.04 0.03 0.84 1.13 0.32 2.07 1.67 1.95 2.34 ns 8 ma std. 0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14 ns ?1 0.51 2.32 0.04 0.96 129 0.36 2.36 1.90 2.22 2.67 ns ?2 0.45 2.04 0.03 0.84 1.13 0.32 2.07 1.67 1.95 2.34 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-25 3.3 v lvcmos wide range table 2-33 ? minimum and maximum dc input and output levels for 3.3 v lvcmos wide range 3.3 v lvcmos wide range equivalent software default drive strength option 3 vil vih vol voh iol i oh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmamaa 4 a 4 100 a 2 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 10 10 100 a 4 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 10 10 100 a 6 ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 10 10 100 a 8ma ?0.3 0.8 2 3.6 0.2 vdd ? 0.2 100 100 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 4. currents are measured at 85c junction temperature. 5. all lvmcos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd8-b specification. 6. software default selection highlighted in gray.
proasic3 nano dc and switching characteristics 2-26 revision 11 timing characteristics table 2-34 ? 3.3 v lvcmos wide range low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.7 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std. 0.60 14.73 0.04 1.57 2.18 0.43 14.73 13.16 3.26 3.38 ns ?1 0.51 12.53 0.04 1.33 1.85 0. 36 12.53 11.19 2.77 2.87 ns ?2 0.45 11.00 0.03 1.17 1.62 0.32 11.00 9.83 2.43 2.52 ns 100 a 4 ma std. 0.60 14.73 0.04 1.57 2.18 0.43 14.73 13.16 3.26 3.38 ns ?1 0.51 12.53 0.04 1.33 1.85 0. 36 12.53 11.19 2.77 2.87 ns ?2 0.45 11.00 0.03 1.17 1.62 0.32 11.00 9.83 2.43 2.52 ns 100 a 6 ma std. 0.60 10.38 0.04 1.57 2.18 0.43 10.38 9.21 3.72 4.16 ns ?1 0.51 8.83 0.04 1.33 1.85 0.36 8.83 7.83 3.17 3.54 ns ?2 0.45 7.75 0.03 1.17 1.62 0.32 7.75 6.88 2.78 3.11 ns 100 a 8 ma std. 0.60 10.38 0.04 1.57 2.18 0.43 10.38 9.21 3.72 4.16 ns ?1 0.51 8.83 0.04 1.33 1.85 0.36 8.83 7.83 3.17 3.54 ns ?2 0.45 7.75 0.03 1.17 1.62 0.32 7.75 6.88 2.78 3.11 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-27 table 2-35 ? 3.3 v lvcmos wide range high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.7 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std. 0.60 10.83 0.04 1.57 2.18 0.43 10.83 9.48 3.25 3.56 ns ?1 0.51 9.22 0.04 1.33 1.85 0.36 9.22 8.06 2.77 3.03 ns ?2 0.45 8.09 0.03 1.17 1.62 0.32 8.09 7.08 2.43 2.66 ns 100 a 4 ma std. 0.60 10.83 0.04 1.57 2.18 0.43 10.83 9.48 3.25 3.56 ns ?1 0.51 9.22 0.04 1.33 1.85 0.36 9.22 8.06 2.77 3.03 ns ?2 0.45 8.09 0.03 1.17 1.62 0.32 8.09 7.08 2.43 2.66 ns 100 a 6 ma std. 0.60 6.78 0.04 1. 57 2.18 0.43 6.78 5.72 3.72 4.35 ns ?1 0.51 5.77 0.04 1.33 1.85 0.36 5.77 4.87 3.16 3.70 ns ?2 0.45 5.06 0.03 1.17 1.62 0.32 5.06 4.27 2.78 3.25 ns 100 a 8 ma std. 0.60 6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35 ns ?1 0.51 5.77 0.04 1.33 1.85 0.36 5.77 4.87 3.16 3.70 ns ?2 0.45 5.06 0.03 1.17 1.62 0.32 5.06 4.27 2.78 3.25 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. 3. software default selection highlighted in gray.
proasic3 nano dc and switching characteristics 2-28 revision 11 table 2-36 ? 3.3 v lvcmos wide range low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.7 v software default load at 35 pf for a3pn020, a3pn015, a3pn010 drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std. 0.60 8.20 0.04 1. 57 2.18 0.43 8.20 7.68 3.26 3.38 ns ?1 0.51 6.97 0.04 1.33 1.85 0.36 6.97 6.53 2.77 2.87 ns ?2 0.45 6.12 0.03 1.17 1.62 0.32 6.12 5.73 2.43 2.52 ns 100 a 4 ma std. 0.60 8.20 0.04 1. 57 2.18 0.43 8.20 7.68 3.26 3.38 ns ?1 0.51 6.97 0.04 1.33 1.85 0.36 6.97 6.53 2.77 2.87 ns ?2 0.45 6.12 0.03 1.17 1.62 0.32 6.12 5.73 2.43 2.52 ns 100 a 6 ma std. 0.60 6.42 0.04 1. 57 2.18 0.43 6.42 6.05 3.72 4.16 ns ?1 0.51 5.46 0.04 1.33 1.85 0.36 5.46 5.14 3.17 3.54 ns ?2 0.45 4.79 0.03 1.17 1.62 0.32 4.79 4.52 2.78 3.11 ns 100 a 8 ma std. 0.60 6.42 0.04 1. 57 2.18 0.43 6.42 6.05 3.72 4.16 ns ?1 0.51 5.46 0.04 1.33 1.85 0.36 5.46 5.14 3.17 3.54 ns ?2 0.45 4.79 0.03 1.17 1.62 0.32 4.79 4.52 2.78 3.11 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-29 table 2-37 ? 3.3 v lvcmos wide range high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.7 v software default load at 35 pf for a3pn020, a3pn015, a3pn010 drive strength equivalent software default drive strength option 1 speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 100 a 2 ma std. 0.60 5.23 0.04 1. 57 2.18 0.43 5.23 4.37 3.25 3.56 ns ?1 0.51 4.45 0.04 1.33 1.85 0.36 4.45 3.71 2.77 3.03 ns ?2 0.45 3.90 0.03 1.17 1.62 0.32 3.90 3.26 2.43 2.66 ns 100 a 4 ma std. 0.60 5.23 0.04 1. 57 2.18 0.43 5.23 4.37 3.25 3.56 ns ?1 0.51 4.45 0.04 1.33 1.85 0.36 4.45 3.71 2.77 3.03 ns ?2 0.45 3.90 0.03 1.17 1.62 0.32 3.90 3.26 2.43 2.66 ns 100 a 6 ma std. 0.60 3.94 0.04 1. 57 2.18 0.43 3.94 3.16 3.72 4.35 ns ?1 0.51 3.35 0.04 1.33 1.85 0.36 3.35 2.69 3.16 3.70 ns ?2 0.45 2.94 0.03 1.17 1.62 0.32 2.94 2.36 2.78 3.25 ns 100 a 8 ma std. 0.60 3.94 0.04 1.57 2.18 0.43 3.94 3.16 3.72 4.35 ns ?1 0.51 3.35 0.04 1.33 1.85 0.36 3.35 2.69 3.16 3.70 ns ?2 0.45 2.94 0.03 1.17 1.62 0.32 2.94 2.36 2.78 3.25 ns notes: 1. the minimum drive strength for any lvcmos 3.3 v software configuration when run in wide range is 100 a. drive strength displayed in the software is supported for normal range only. for a detailed i/v curve, refer to the ibis models. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. 3. software default selection highlighted in gray.
proasic3 nano dc and switching characteristics 2-30 revision 11 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. table 2-38 ? minimum and maximum dc input and output levels 2.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.7 1.7 3. 6 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 3.6 0. 7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 3. 6 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (1 00c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-7 ? ac loading table 2-39 ? 2.5 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.210 notes: 1. measuring point = vtrip. see table 2-16 on page 2-17 for a complete table of trip points. 2. capacitive load for a3pn060, a3pn125, and a3pn250 is 35 pf. test point test point enable path datapath 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 35 pf for t hz / t lz
proasic3 nano flash fpgas revision 11 2-31 timing characteristics table 2-40 ? 2.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 11.29 0.04 1.43 1.6 3 0.43 10.64 11.29 2.27 2.29 ns ?1 0.51 9.61 0.04 1.22 1.39 0.36 9.05 9.61 1.93 1.95 ns ?2 0.45 8.43 0.03 1.07 1.22 0.32 7.94 8.43 1.70 1.71 ns 4 ma std. 0.60 11.29 0.04 1.43 1.6 3 0.43 10.64 11.29 2.27 2.29 ns ?1 0.51 9.61 0.04 1.22 1.39 0.36 9.05 9.61 1.93 1.95 ns ?2 0.45 8.43 0.03 1.07 1.22 0.32 7.94 8.43 1.70 1.71 ns 6 ma std. 0.60 7.73 0.04 1.43 1. 63 0.43 7.70 7.73 2.60 2.89 ns ?1 0.51 6.57 0.04 1.22 1.39 0.36 6.55 6.57 2.21 2.46 ns ?2 0.45 5.77 0.03 1.07 1.22 0.32 5.75 5.77 1.94 2.16 ns 8 ma std. 0.60 7.73 0.04 1.43 1. 63 0.43 7.70 7.73 2.60 2.89 ns ?1 0.51 6.57 0.04 1.22 1.39 0.36 6.55 6.57 2.21 2.46 ns ?2 0.45 5.77 0.03 1.07 1.22 0.32 5.75 5.77 1.94 2.16 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-41 ? 2.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 8.38 0.04 1.43 1. 63 0.43 7.36 8.38 2.27 2.37 ns ?1 0.51 7.13 0.04 1.22 1.39 0.36 6.26 7.13 1.93 2.02 ns ?2 0.45 6.26 0.03 1.07 1.22 0.32 5.50 6.26 1.69 1.77 ns 4 ma std. 0.60 8.38 0.04 1.43 1. 63 0.43 7.36 8.38 2.27 2.37 ns ?1 0.51 7.13 0.04 1.22 1.39 0.36 6.26 7.13 1.93 2.02 ns ?2 0.45 6.26 0.03 1.07 1.22 0.32 5.50 6.26 1.69 1.77 ns 6 ma std. 0.60 4.94 0.04 1.43 1. 63 0.43 4.71 4.94 2.60 2.98 ns ?1 0.51 4.20 0.04 1.22 1.39 0.36 4.01 4.20 2.21 2.54 ns ?2 0.45 3.69 0.03 1.07 1.22 0.32 3.52 3.69 1.94 2.23 ns 8 ma std. 0.60 4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98 ns ?1 0.51 4.20 0.04 1.22 1.39 0.36 4.01 4.20 2.21 2.54 ns ?2 0.45 3.69 0.03 1.07 1.22 0.32 3.52 3.69 1.94 2.23 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-32 revision 11 table 2-42 ? 2.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 6.40 0.04 1.43 1. 63 0.43 6.16 6.40 2.27 2.29 ns ?1 0.51 5.45 0.04 1.22 1.39 0.36 5.24 5.45 1.93 1.95 ns ?2 0.45 4.78 0.03 1.07 1.22 0.32 4.60 4.78 1.70 1.71 ns 4 ma std. 0.60 6.40 0.04 1.43 1. 63 0.43 6.16 6.40 2.27 2.29 ns ?1 0.51 5.45 0.04 1.22 1.39 0.36 5.24 5.45 1.93 1.95 ns ?2 0.45 4.78 0.03 1.07 1.22 0.32 4.60 4.78 1.70 1.71 ns 6 ma std. 0.60 5.00 0.04 1.43 1. 63 0.43 4.90 5.00 2.60 2.89 ns ?1 0.51 4.26 0.04 1.22 1.39 0.36 4.17 4.26 2.21 2.46 ns ?2 0.45 3.74 0.03 1.07 1.22 0.32 3.66 3.74 1.94 2.16 ns 8 ma std. 0.60 5.00 0.04 1.43 1. 63 0.43 4.90 5.00 2.60 2.89 ns ?1 0.51 4.26 0.04 1.22 1.39 0.36 4.17 4.26 2.21 2.46 ns ?2 0.45 3.74 0.03 1.07 1.22 0.32 3.66 3.74 1.94 2.16 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-43 ? 2.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 2.3 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 3.70 0.04 1.43 1. 63 0.43 3.66 3.70 2.27 2.37 ns ?1 0.51 3.15 0.04 1.22 1.39 0.36 3.12 3.15 1.93 2.02 ns ?2 0.45 2.77 0.03 1.07 1.22 0.32 2.74 2.77 1.69 1.77 ns 4 ma std. 0.60 3.70 0.04 1.43 1. 63 0.43 3.66 3.70 2.27 2.37 ns ?1 0.51 3.15 0.04 1.22 1.39 0.36 3.12 3.15 1.93 2.02 ns ?2 0.45 2.77 0.03 1.07 1.22 0.32 2.74 2.77 1.69 1.77 ns 6 ma std. 0.60 2.76 0.04 1.43 1. 63 0.43 2.80 2.60 2.60 2.98 ns ?1 0.51 2.35 0.04 1.22 1.39 0.36 2.38 2.21 2.21 2.54 ns ?2 0.45 2.06 0.03 1.07 1.22 0.32 2.09 1.94 1.94 2.23 ns 8 ma std. 0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98 ns ?1 0.51 2.35 0.04 1.22 1.39 0.36 2.38 2.21 2.21 2.54 ns ?2 0.45 2.06 0.03 1.07 1.22 0.32 2.09 1.94 1.94 2.23 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-33 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standa rd (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-44 ? minimum and maximum dc input and output levels 1.8 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.45 vcci ? 0.45 4 4 17 22 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-8 ? ac loading table 2-45 ? 1.8 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.910 notes: 1. measuring point = vtrip. see table 2-16 on page 2-17 for a complete table of trip points. 2. capacitive load for a3pn060, a3pn125, and a3pn250 is 35 pf. test point test point enable path datapath 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 35 pf for t hz / t lz
proasic3 nano dc and switching characteristics 2-34 revision 11 timing characteristics table 2-46 ? 1.8 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 15.36 0.04 1.35 1.9 0 0.43 13.46 15.36 2.23 1.78 ns ?1 0.51 13.07 0.04 1.15 1.61 0.36 11.45 13.07 1.90 1.51 ns ?2 0.45 11.47 0.03 1.01 1.42 0 .32 10.05 11.47 1.67 1.33 ns 4 ma std. 0.60 10.32 0.04 1.35 1.90 0.43 9.92 10.32 2.63 2.78 ns ?1 0.51 8.78 0.04 1.15 1.61 0.36 8.44 8.78 2.23 2.37 ns ?2 0.45 7.71 0.03 1.01 1.42 0.32 7.41 7.71 1.96 2.08 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-47 ? 1.8 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 11.42 0.04 1.35 1.90 0.43 8.65 11.42 2.23 1.84 ns ?1 0.51 9.71 0.04 1.15 1.61 0.36 7.36 9.71 1.89 1.57 ns ?2 0.45 8.53 0.03 1.01 1.42 0.32 6.46 8.53 1.66 1.37 ns 4 ma std. 0.60 6.53 0.04 1.35 1.90 0.43 5.53 6.53 2.62 2.89 ns ?1 0.51 5.56 0.04 1.15 1.61 0.36 4.70 5.56 2.23 2.45 ns ?2 0.45 4.88 0.03 1.01 1.42 0.32 4.13 4.88 1.96 2.15 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-35 table 2-48 ? 1.8 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 8.52 0.04 1.35 1. 90 0.43 7.99 8.52 2.23 1.78 ns ?1 0.51 7.25 0.04 1.15 1.61 0.36 6.80 7.25 1.90 1.51 ns ?2 0.45 6.36 0.03 1.01 1.42 0.32 5.97 6.36 1.67 1.33 ns 4 ma std. 0.60 6.59 0.04 1.35 1. 90 0.43 6.44 6.59 2.63 2.78 ns ?1 0.51 5.60 0.04 1.15 1.61 0.36 5.48 5.60 2.23 2.37 ns ?2 0.45 4.92 0.03 1.01 1.42 0.32 4.81 4.92 1.96 2.08 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-49 ? 1.8 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.7 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 4.79 0.04 1.35 1. 90 0.43 4.27 4.79 2.23 1.84 ns ?1 0.51 4.08 0.04 1.15 1.61 0.36 3.63 4.08 1.89 1.57 ns ?2 0.45 3.58 0.03 1.01 1.42 0.32 3.19 3.58 1.66 1.37 ns 4 ma std. 0.60 3.22 0.04 1.35 1.90 0.43 3.24 3.22 2.62 2.89 ns ?1 0.51 2.74 0.04 1.15 1.61 0.36 2.75 2.74 2.23 2.45 ns ?2 0.45 2.40 0.03 1.01 1.42 0.32 2.42 2.40 1.95 2.15 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-36 revision 11 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-50 ? minimum and maximum dc input and output levels 1.5 v lvcmos vil vih vol voh iol ioh iosl iosh iil 1 iih 2 drive strength min. v max. v min. v max. v max. v min. vmama max. ma 3 max. ma 3 a 4 a 4 2 ma ?0.3 0.35 * vcci 0.65 * vcci 3.6 0.25 * vcci 0.75 * vcci 2 2 13 16 10 10 notes: 1. iil is the input leakage current per i/o pin over recommended operation conditions where ?0.3 v < vin < vil. 2. iih is the input leakage current per i/o pin over recommended operating conditions vih < vin < vcci. input current is larger when operating outside recommended ranges. 3. currents are measured at high temperature (100 c junction temperature) and maximum voltage. 4. currents are measured at 85c junction temperature. 5. software default selection highlighted in gray. figure 2-9 ? ac loading table 2-51 ? 1.5 v lvcmos ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 1.5 0.75 10 notes: 1. measuring point = vtrip. see table 2-16 on page 2-17 for a complete table of trip points. 2. capacitive load for a3pn060, a3pn125, and a3pn250 is 35 pf. test point test point enable path datapath 35 pf r = 1 k r to vcci for t lz / t zl / t zls r to gnd for t hz / t zh / t zhs 35 pf for t zh / t zhs / t zl / t zls 35 pf for t hz / t lz
proasic3 nano flash fpgas revision 11 2-37 timing characteristics table 2-52 ? 1.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 12.58 0.04 1.56 2.1 4 0.43 12.18 12.58 2.67 2.71 ns ?1 0.51 10.70 0.04 1.32 1.82 0 .36 10.36 10.70 2.27 2.31 ns ?2 0.45 9.39 0.03 1.16 1.59 0.32 9.09 9.39 1.99 2.03 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-53 ? 1.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v software default load at 35 pf for a3pn060, a3pn125, a3pn250 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 7.86 0.04 1.56 2.14 0.43 6.45 7.86 2.66 2.83 ns ?1 0.51 6.68 0.04 1.32 1.82 0.36 5.49 6.68 2.26 2.41 ns ?2 0.45 5.87 0.03 1.16 1.59 0.32 4.82 5.87 1.99 2.12 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-54 ? 1.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 8.01 0.04 1.56 2. 14 0.43 8.03 8.01 2.67 2.71 ns ?1 0.51 6.81 0.04 1.32 1.82 0.36 6.83 6.81 2.27 2.31 ns ?2 0.45 5.98 0.03 1.16 1.58 0.32 6.00 5.98 2.10 2.03 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-55 ? 1.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 1.4 v software default load at 10 pf for a3pn020, a3pn015, a3pn010 drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std. 0.60 3.76 0.04 1.52 2.14 0.43 3.74 3.76 2.66 2.83 ns ?1 0.51 3.20 0.04 1.32 1.82 0.36 3.18 3.20 2.26 2.41 ns ?2 0.45 2.81 0.03 1.16 1.59 0.32 2.79 2.81 1.99 2.12 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-38 revision 11 i/o register specifications fully registered i/o buffers with synchronous enable and asynchronous preset figure 2-10 ? timing model of registered i/o buffers with synchronous enable and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive-edge triggered data output register and enable output register with: active high enable active high preset postive-edge triggered pad out clk enable preset data_out data eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
proasic3 nano flash fpgas revision 11 2-39 table 2-56 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of the output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the output enable register j, h t oesue enable setup time for the output enable register k, h t oehe enable hold time for the output enable register k, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time for the output enable register i, h t oerecpre asynchronous preset recovery time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of th e input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a note: *see figure 2-10 on page 2-38 for more information.
proasic3 nano dc and switching characteristics 2-40 revision 11 fully registered i/o buffers with synchronous enable and asynchronous clear figure 2-11 ? timing model of the registered i/o buffers with synchronous enable and asynchronous clear enable clk pad out clk enable clr data_out data y aa eout dout core array dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_enable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf data input i/o register with active high enable active high clear positive-edge triggered data output register and enable output register with active high enable active high clear positive-edge triggered
proasic3 nano flash fpgas revision 11 2-41 table 2-57 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the output enable register kk, hh t oehe enable hold time for the output enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa note: *see figure 2-11 on page 2-40 for more information.
proasic3 nano dc and switching characteristics 2-42 revision 11 input register timing characteristics figure 2-12 ? input register timing diagram 50% preset clear out_1 clk data enable t isue 50% 50% t isud t ihd 50% 50% t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-58 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t iclkq clock-to-q of the input data register 0.24 0.27 0.32 ns t isud data setup time for the input data register 0.26 0.30 0.35 ns t ihd data hold time for the input data register 0.00 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the in put data register 0.45 0.52 0.61 ns t ipre2q asynchronous preset-to-q of the i nput data register 0.45 0.52 0.61 ns t iremclr asynchronous clear removal time for the input data regi ster 0.00 0.00 0.00 ns t irecclr asynchronous clear recovery time for the input data regi ster 0.22 0.25 0.30 ns t irempre asynchronous preset removal time for the input data register 0.00 0.00 0.00 ns t irecpre asynchronous preset recovery time fo r the input data r egister 0.22 0.25 0.30 ns t iwclr asynchronous clear minimum pulse width fo r the input data register 0.22 0.25 0.30 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.22 0.25 0.30 ns t ickmpwh clock minimum pulse width high for the input data register 0.36 0.41 0.48 ns t ickmpwl clock minimum pulse width low for t he input data register 0.32 0.37 0.43 ns note: for specific junction te mperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-43 output register timing characteristics figure 2-13 ? output register timing diagram preset clear dout clk data_out enable t osue 50% 50% t osud t ohd 50% 50% t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-59 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t oclkq clock-to-q of the output data register 0.59 0.67 0.79 ns t osud data setup time for the output data register 0.31 0.36 0.42 ns t ohd data hold time for the output data register 0.00 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the out put data register 0.80 0.91 1.07 ns t opre2q asynchronous preset-to-q of the ou tput data register 0.80 0.91 1.07 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 0.00 ns t orecclr asynchronous clear recovery time for t he output data register 0.22 0.25 0.30 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.22 0.25 0.30 ns t owclr asynchronous clear minimum pulse width for the output data register 0.22 0.25 0.30 ns t owpre asynchronous preset minimum pulse width for the output data register 0.22 0.25 0.30 ns t ockmpwh clock minimum pulse width high for the output data register 0.36 0.41 0.48 ns t ockmpwl clock minimum pulse width low for the output data register 0.32 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-44 revision 11 output enable register timing characteristics figure 2-14 ? output enable register timing diagram 50% preset clear eout clk d_enable enable t oesue 50% 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-60 ? output enable register propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t oeclkq clock-to-q of the output en able register 0.44 0.51 0.59 ns t oesud data setup time for the output enable register 0.31 0.36 0.42 ns t oehd data hold time for the output enable register 0.00 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the out put enable register 0.67 0.76 0.89 ns t oepre2q asynchronous preset-to-q of the ou tput enable register 0.67 0.76 0.89 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 0.00 0.00 ns t oerecclr asynchronous clear recovery time for t he output enable register 0.22 0.25 0.30 ns t oerempre asynchronous preset removal time for th e output enable register 0.00 0.00 0.00 ns t oerecpre asynchronous preset recovery time for t he output enable register 0.22 0.25 0.30 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.22 0.25 0.30 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.22 0.25 0.30 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.36 0.41 0.48 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.32 0.37 0.43 ns note: for specific junction te mperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-45 ddr module specifications input ddr module figure 2-15 ? input ddr timing model table 2-61 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core)
proasic3 nano dc and switching characteristics 2-46 revision 11 timing characteristics figure 2-16 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-62 ? input ddr propagation delays commercial-case conditions: t j = 70c, worst case vcc = 1.425 v parameter description ?2 ?1 std. units t ddriclkq1 clock-to-out out_qr for input ddr 0.27 0.31 0.37 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.39 0.44 0.52 ns t ddrisud data setup for input ddr (fall) 0.28 0.32 0.38 ns data setup for input ddr (rise) 0.25 0.28 0.33 ns t ddrihd data hold for input ddr (fall) 0.00 0.00 0.00 ns data hold for input ddr (rise) 0.00 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_ qr for input ddr 0.46 0.53 0.62 ns t ddriclr2q2 asynchronous clear-to-out out_ qf for input ddr 0.57 0.65 0.76 ns t ddriremclr asynchronous clear removal ti me for input ddr 0.00 0.00 0.00 ns t ddrirecclr asynchronous clear recovery ti me for input dd r 0.22 0.25 0.30 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.22 0.25 0.30 ns t ddrickmpwh clock minimum pulse width hig h for input ddr 0.36 0.41 0.48 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.32 0.37 0.43 ns f ddrimax maximum frequency for input ddr 350.00 350.00 350.00 mhz note: for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-47 output ddr module figure 2-17 ? output ddr timing model table 2-63 ? parameter definitions parameter name parameter definition measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x a b d e c c b outbuf data_r (from core)
proasic3 nano dc and switching characteristics 2-48 revision 11 timing characteristics figure 2-18 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddroremclr t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-64 ? output ddr propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t ddroclkq clock-to-out of ddr for output ddr 0.70 0.80 0.94 ns t ddrosud1 data_f data setup for output ddr 0.38 0.43 0.51 ns t ddrosud2 data_r data setup for output ddr 0.38 0.43 0.51 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out fo r output ddr 0.80 0.91 1.07 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.22 0.25 0.30 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr 0.22 0.25 0.30 ns t ddrockmpwh clock minimum pulse width high for the output ddr 0.36 0.41 0.48 ns t ddrockmpwl clock minimum pulse width low fo r the output ddr 0.32 0.37 0.43 ns f ddomax maximum frequency for the output ddr 350.00 350.00 350.00 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-49 versatile characteristics versatile specifications as a combinatorial module the proasic3 library offers all combinations of lut- 3 combinatorial functions. in this section, timing characteristics are presented for a sample of the library. for more details, refer to the fusion, igloo ? /e, and proasic3/e macro library guide . figure 2-19 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
proasic3 nano dc and switching characteristics 2-50 revision 11 figure 2-20 ? timing model and waveforms t pd a b t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for the particular combinatorial cell y nand2 or any combinatorial logic t pd t pd 50% vcc vcc vcc 50% gnd a, b, c 50% 50% 50% (rr) (rf) gnd out out gnd 50% (ff) (fr) t pd t pd
proasic3 nano flash fpgas revision 11 2-51 timing characteristics versatile specifications as a sequential module the proasic3 library offers a wide variety of sequentia l cells, including flip-flops and latches. each has a data input and optional enable, clear, or preset. in this section, timing characteristics are presented for a representative sample from the library. for more details, refer to the fusion, igloo/e, and proasic3/e macro library guide . table 2-65 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v combinatorial cell equation parameter ?2 ?1 std. units inv y = !a t pd 0.40 0.46 0.54 ns and2 y = a b t pd 0.47 0.54 0.63 ns nand2 y = !(a b) t pd 0.47 0.54 0.63 ns or2 y = a + b t pd 0.49 0.55 0.65 ns nor2 y = !(a + b) t pd 0.49 0.55 0.65 ns xor2 y = a ?? bt pd 0.74 0.84 0.99 ns maj3 y = maj(a, b, c) t pd 0.70 0.79 0.93 ns xor3 y = a ? b ?? ct pd 0.87 1.00 1.17 ns mux2 y = a !s + b s t pd 0.51 0.58 0.68 ns and3 y = a b c t pd 0.56 0.64 0.75 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. figure 2-21 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
proasic3 nano dc and switching characteristics 2-52 revision 11 timing characteristics figure 2-22 ? timing model and waveforms pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-66 ? register delays commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t clkq clock-to-q of the core register 0.55 0.63 0.74 ns t sud data setup time for the core register 0.43 0.49 0.57 ns t hd data hold time for the core register 0.00 0.00 0.00 ns t sue enable setup time for the core register 0.45 0.52 0.61 ns t he enable hold time for the core register 0.00 0.00 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.40 0.45 0.53 ns t pre2q asynchronous preset-to-q of t he core register 0.40 0.45 0.53 ns t remclr asynchronous clear removal time for the core register 0.00 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.22 0.25 0.30 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.22 0.25 0.30 ns t wclr asynchronous clear minimum pulse width for the core register 0.22 0.25 0.30 ns t wpre asynchronous preset minimum pulse width for the core register 0.22 0.25 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.36 0.41 0.48 ns t ckmpwl clock minimum pulse width low for the core register 0.32 0.37 0.43 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-53 global resource characteristics a3pn250 clock tree topology clock delays are device-specific. figure 2-23 is an example of a global tree used for clock routing. the global tree presented in figure 2-23 is driven by a ccc located on the west side of the a3pn250 device. it is used to drive all d- flip-flops in the device. figure 2-23 ? example of global tree use in an a3pn250 device for clock routing central global rib versatile rows global spine ccc
proasic3 nano dc and switching characteristics 2-54 revision 11 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-57 . ta b l e 2 - 6 7 to table 2-72 on page 2-56 present minimum and maximum global clock delays within each device. minimum and maximum delays are measured with minimum and maximum loading. timing characteristics table 2-67 ? a3pn010 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.60 0.79 0.69 0.90 0.81 1.06 ns t rckh input high delay for global clock 0.62 0.84 0.70 0.96 0.82 1.12 ns t rckmpwh minimum pulse width high for global clock 0.75 0.85 1.00 ns t rckmpwl minimum pulse width low for global clock 0.85 0.96 1.13 ns t rcksw maximum skew for global clock 0.22 0.26 0.30 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-68 ? a3pn015 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.66 0.91 0.75 1.04 0.89 1.22 ns t rckh input high delay for global clock 0.67 0.96 0.77 1.10 0.90 1.29 ns t rckmpwh minimum pulse width high for global clock 0.75 0.85 1.00 ns t rckmpwl minimum pulse width low for global clock 0.85 0.96 1.13 ns t rcksw maximum skew for global clock 0.29 0.33 0.39 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-55 table 2-69 ? a3pn020 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.66 0.91 0.75 1.04 0.89 1.22 ns t rckh input high delay for global clock 0.67 0.96 0.77 1.10 0.90 1.29 ns t rckmpwh minimum pulse width high for global clock 0.75 0.85 1.00 ns t rckmpwl minimum pulse width low for global clock 0.85 0.96 1.13 ns t rcksw maximum skew for global clock 0.29 0.33 0.39 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-70 ? a3pn060 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.72 0.91 0.82 1.04 0.96 1.22 ns t rckh input high delay for global clo ck 0.71 0.94 0.81 1.07 0.96 1.26 ns t rckmpwh minimum pulse width high for global clock 0.75 0.85 1.00 ns t rckmpwl minimum pulse width low for global clock 0.85 0.96 1.13 ns t rcksw maximum skew for global clock 0.23 0.26 0.31 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-56 revision 11 table 2-71 ? a3pn125 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.76 0.99 0.87 1.12 1.02 1.32 ns t rckh input high delay for global clock 0.76 1.02 0.87 1.17 1.02 1.37 ns t rckmpwh minimum pulse width high for global clock 0.75 0.85 1.00 ns t rckmpwl minimum pulse width low for global clock 0.85 0.96 1.13 ns t rcksw maximum skew for global clock 0.26 0.30 0.35 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values. table 2-72 ? a3pn250 global resource commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?2 ?1 std. units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.79 1.02 0.90 1.16 1.06 1.36 ns t rckh input high delay for global clock 0.78 1.04 0.88 1.18 1.04 1.39 ns t rckmpwh minimum pulse width high for global clock 0.75 0.85 1.00 ns t rckmpwl minimum pulse width low for global clock 0.85 0.96 1.13 ns t rcksw maximum skew for global clock 0.26 0.30 0.35 ns notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano flash fpgas revision 11 2-57 clock conditioning circuits ccc electrical specifications timing characteristics table 2-73 ? proasic3 nano ccc/pll specification parameter minimum typical maximum units clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 mhz delay increments in programmable delay blocks 1,2 200 3 ps number of programmable values in each programmable delay block 32 serial clock (sclk) for dynamic pll 4,5 125 mhz input cycle-to-cycle jitter (peak magnitude) 1.5 ns acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 7 lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1,2 1.25 15.65 ns delay range in block: programmable delay 2 1,2 0.025 15.65 ns delay range in block: fixed delay 1,2 2.2 ns vco output peak-to-peak period jitter f ccc_out 6 max peak-to-peak jitter data 6,8,9 sso ?? ? 2 sso ?? ? 4 sso ? ? 8sso ?? 16 0.75 mhz to 50mhz 0.50% 0.50% 0.70% 1.00% 50 mhz to 250 mhz 1.00% 3.00% 5.00% 9.00% 250 mhz to 350 mhz 2.50% 4.00% 6.00% 12.00% notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-5 for deratings. 2. t j = 25c, vcc = 1.5 v 3. when the ccc/pll core is generated by microsemi core generator software, not all delay values of the specified delay increments are available. refer to the libero soc online help for more information. 4. maximum value obtained for a ?2 speed-grade device in worst-case commercial conditions. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values. 5. the a3pn010, a3pn015, and a3pn020 devices do not support plls. 6. vco output jitter is calculated as a percentage of the vco frequency. the jitter (in ps) can be calculated by multiplying the vco period by the % jitter. the vco jitter (in ps) applies to ccc_out regardless of the output divider settings. for example, if the jitter on vco is 300 ps, the jitter on ccc_out is also 300 ps, regardless of the output divider settings. 7. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to the pll input clock edge. tracking jitter does not measure the variation in pll output period, which is covered by the period jitter parameter. 8. measurements done with lvttl 3.3 v 8 ma i/o drive strength and high slew rate. vcc/vccpll = 1.425 v, vcci = 3.3 , vq/pq/tq type of packages, 20 pf load. 9. ssos are outputs that are synchronous to a single clock domain, and have their clock-to-out times within 200 ps of each other.
proasic3 nano dc and switching characteristics 2-58 revision 11 note: peak-to-peak jitter meas urements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-24 ? peak-to-peak jitter definition t period_max t period_min output signal
proasic3 nano flash fpgas revision 11 2-59 embedded sram and fifo characteristics sram figure 2-25 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
proasic3 nano dc and switching characteristics 2-60 revision 11 timing waveforms figure 2-26 ? ram read for pass-through output. applicable to both ram4k9 and ram512x18. figure 2-27 ? ram read for pipelined output. appl icable to both ram4k9 and ram512x18. clk [r|w]addr blk wen dout|rd a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk [r|w]addr blk wen dout|rd a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
proasic3 nano flash fpgas revision 11 2-61 figure 2-28 ? ram write, output retained. applicable to both ram4k9 and ram512x18. figure 2-29 ? ram write, output as write data (wmode = 1). applicable to both ram4k9 only. t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk wen [r|w]addr din|wd d n dout|rd t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk wen addr din t bkh dout (pass-through) di 1 d n di 0 dout (pipelined) di 0 di 1 d n di 2
proasic3 nano dc and switching characteristics 2-62 revision 11 figure 2-30 ? ram reset. applicable to both ram4k9 and ram512x18. clk reset dout|rd d n t cyc t ckh t ckl t rstbq d m
proasic3 nano flash fpgas revision 11 2-63 timing characteristics table 2-74 ? ram4k9 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t as address setup time 0.25 0.28 0.33 ns t ah address hold time 0.00 0.00 0.00 ns t ens ren, wen setup time 0.14 0.16 0.19 ns t enh ren, wen hold time 0.10 0.11 0.13 ns t bks blk setup time 0.23 0.27 0.31 ns t bkh blk hold time 0.02 0.02 0.02 ns t ds input data (din) setup time 0.18 0.21 0.25 ns t dh input data (din) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on dout (output retained, wmode = 0) 1.79 2.03 2.39 ns clock high to new data valid on dout (flow-through, wmode = 1) 2.36 2.68 3.15 ns t ckq2 clock high to new data valid on dout (pipelined) 0.89 1.02 1.20 ns t c2cwwl 1 address collision clk-to-clk delay for reliable write after write on same address; applicable to closing edge 0.33 0.28 0.25 ns t c2cwwh 1 address collision clk-to-clk delay for reliable write after write on same address; applicable to rising edge 0.30 0.26 0.23 ns t c2crwh 1 address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.45 0.38 0.34 ns t c2cwrh 1 address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 0.49 0.42 0.37 ns t rstbq reset low to data out low on dout (flow through) 0.92 1.05 1.23 ns reset low to data out low on dout (pipelined) 0.92 1.05 1.23 ns t remrstb reset removal 0.29 0.33 0.38 ns t recrstb reset recovery 1.50 1.71 2.01 ns t mpwrstb reset minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency 310 272 231 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 nano dc and switching characteristics 2-64 revision 11 table 2-75 ? ram512x18 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t as address setup time 0.25 0.28 0.33 ns t ah address hold time 0.00 0.00 0.00 ns t ens ren, wen setup time 0.09 0.10 0.12 ns t enh ren, wen hold time 0.06 0.07 0.08 ns t ds input data (wd) setup time 0.18 0.21 0.25 ns t dh input data (wd) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on rd (output retained) 2.16 2.46 2.89 ns t ckq2 clock high to new data valid on rd (pipelined) 0.90 1.02 1.20 ns t c2crwh 1 address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.50 0.43 0.38 ns t c2cwrh 1 address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 0.59 0.50 0.44 ns t rstbq reset low to data out low on rd (flow-through) 0.92 1.05 1.23 ns reset low to data out low on rd (pipelined) 0.92 1.05 1.23 ns t remrstb reset removal 0.29 0.33 0.38 ns t recrstb reset recovery 1.50 1.71 2.01 ns t mpwrstb reset minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency 310 272 231 mhz notes: 1. for more information, refer to the application note simultaneous read-write operations in dual-port sram for flash- based csocs and fpgas . 2. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 nano flash fpgas revision 11 2-65 fifo figure 2-31 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
proasic3 nano dc and switching characteristics 2-66 revision 11 timing waveforms figure 2-32 ? fifo read figure 2-33 ? fifo write t ens t enh t ckq1 t ckq2 t cyc d 0 d 1 d n d n d 0 d 2 d 1 t bks t bkh rclk rblk ren rd (flow-through) rd (pipelined) wclk wen wd t ens t enh t ds t dh t cyc di 0 di 1 t bkh t bks wblk
proasic3 nano flash fpgas revision 11 2-67 figure 2-34 ? fifo reset figure 2-35 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
proasic3 nano dc and switching characteristics 2-68 revision 11 figure 2-36 ? fifo full flag and afull flag assertion figure 2-37 ? fifo empty flag and aempty flag deassertion figure 2-38 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
proasic3 nano flash fpgas revision 11 2-69 timing characteristics table 2-76 ? fifo worst commercial-case conditions: t j = 70c, vcc = 1.425 v parameter description ?2 ?1 std. units t ens ren, wen setup time 1.38 1.57 1.84 ns t enh ren, wen hold time 0.02 0.02 0.02 ns t bks blk setup time 0.22 0.25 0.30 ns t bkh blk hold time 0.00 0.00 0.00 ns t ds input data (wd) setup time 0.18 0.21 0.25 ns t dh input data (wd) hold time 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on rd (flow-through) 2.36 2.68 3.15 ns t ckq2 clock high to new data valid on rd (pipelined) 0.89 1.02 1.20 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 ns t ckaf clock high to almost empty/fu ll flag valid 6.19 7.05 8.29 ns t rstfg reset low to empty/full flag valid 1.69 1.93 2.27 ns t rstaf reset low to almost empty/fu ll flag valid 6.13 6.98 8.20 ns t rstbq reset low to data out low on rd (flow-through) 0.92 1.05 1.23 ns reset low to data out low on rd (pipelined) 0.92 1.05 1.23 ns t remrstb reset removal 0.29 0.33 0.38 ns t recrstb reset recovery 1.50 1.71 2.01 ns t mpwrstb reset minimum pulse width 0.21 0.24 0.29 ns t cyc clock cycle time 3.23 3.68 4.32 ns f max maximum frequency for fifo 310 272 231 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-70 revision 11 embedded flashrom characteristics timing characteristics figure 2-39 ? timing diagram a 0 a 1 t su t hold t su t hold t su t hold t ckq2 t ckq2 t ckq2 clk address data d 0 d 0 d 1 table 2-77 ? embedded flashrom access time commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t su address setup time 0.53 0.61 0.71 ns t hold address hold time 0.00 0.00 0.00 ns t ck2q clock to out 16.23 18.48 21.73 ns f max maximum clock frequency 15.00 15.00 15.00 mhz
proasic3 nano flash fpgas revision 11 2-71 jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtai n complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing characteristics in the "user i/o characteristics" section on page 2-12 for more details. timing characteristics table 2-78 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case vcc = 1.425 v parameter description ?2 ?1 std. units t disu test data input setup time 0.53 0.60 0.71 ns t dihd test data input hold time 1.07 1.21 1.42 ns t tmssu test mode select setup time 0.53 0.60 0.71 ns t tmdhd test mode select hold time 1.07 1.21 1.42 ns t tck2q clock to q (data out) 6.39 7.24 8.52 ns t rstb2q reset to q (data out) 21.31 24.15 28.41 ns f tckmax tck maximum frequency 23.00 20.00 17.00 mhz t trstrem resetb removal time 0.00 0.00 0.00 ns t trstrec resetb recovery time 0.21 0.24 0.28 ns t trstmpw resetb minimum pulse tbd tbd tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-5 for derating values.
proasic3 nano dc and switching characteristics 2-72 revision 11
revision 11 3-1 3 ? pin descriptions and packaging supply pins gnd ground ground supply voltage to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. within the package, the gndq plane is decoupled from the simultaneous switching noise orig inated from the output buffer ground domain. this minimizes the noise transfer within the package and im proves input signal integrity. gndq must always be connected to gnd on the board. vcc core supply voltage supply voltage to the fpga core, nominally 1.5 v. v cc is required for powering the jtag state machine in addition to vjtag. even when a device is in by pass mode in a jtag chain of interconnected devices, both vcc and vjtag must remain powered to allow jtag signals to pass through the device. vccibx i/o supply voltage supply voltage to the bank's i/o output buffers and i/o logic. bx is the i/o bank number. there are up to eight i/o banks on low power flash devices plus a dedicated vjtag bank. each bank can have a separate vcci connection. all i/os in a bank will run off the same vccibx supply. vcci can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o ba nks should have their corresponding vcci pins tied to gnd. vmvx i/o supply voltage (quiet) quiet supply voltage to the input buffers of each i/o bank. x is the bank number. within the package, the vmv plane biases the input stage of the i/os in the i/o banks. this minimizes the noise transfer within the package and improves input signal integrity. ea ch bank must have at least one vmv connection, and no vmv should be left unconnected. all i/os in a bank run off the same vmvx supply. vmv is used to provide a quiet supply voltage to the input buffers of each i/o bank. vmvx can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vmv pins tied to gnd. vmv and vcci should be at the same voltage within a gi ven i/o bank. used vmv pins must be connected to the corresponding vcci pins of the same bank (i .e., vmv0 to vccib0, vmv1 to vccib1, etc.). vccpla/b/c/d/e/f pll supply voltage supply voltage to analog pll, nominally 1.5 v. when the plls are not used, the plac e-and-route tool automatically di sables the unused plls to lower power consumption. the user should tie unused v ccplx and vcomplx pins to ground. microsemi recommends tying vccplx to vcc and using proper f iltering circuits to decouple vcc noise from the plls. refer to the pll power supply decoupling section of the "clock conditioning circuits in low power flash devices and mixed signal fpgas" chapter of the proasic3 nano device family user?s guide for a complete board solution for the pll analog power supply and ground. there is one vccplf pin on proasic3 nano devices. vcompla/b/c/d/e/f pll ground ground to analog pll power supplies. when the plls are not used, the place-and-route tool automatically disables the unused plls to lower power consumption. the user should tie unused vccplx and vcomplx pins to ground. there is one vcomplf pin on proasic3 nano devices. vjtag jtag supply voltage low power flash devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). isol ating the jtag power supply in a separate i/o bank
pin descriptions and packaging 3-2 revision 11 gives greater flexibility in supply selection and si mplifies power supply and pcb design. if the jtag interface is neither used nor planned for use, the vj tag pin together with the trst pin could be tied to gnd. it should be noted that vcc is required to be powered for jtag operation; vjtag alone is insufficient. if a device is in a jtag chain of inte rconnected boards, the board containing the device can be powered down, provided both vjtag and vcc to th e part remain powered; otherwise, jtag signals will not be able to transition the device, even in bypass mode. microsemi recommends that vpump and vjtag pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. vpump programming supply voltage proasic3 devices support single-voltage isp of the configuration flash and flashrom. for programming, vpump should be 3.3 v nominal. duri ng normal device operation, vpump can be left floating or can be tied (pulled up) to any voltage between 0 v and the vpump maximum. programming power supply voltage (vpump) range is listed in the datasheet. when the vpump pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. for proper programming, 0.01 f and 0.33 f capacitors (both rated at 16 v) are to be connected in parallel across vpump and gnd, and positioned as close to the fpga pins as possible. microsemi recommends that vpump and vjtag pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. user pins i/o user input/output the i/o pin functions as an input, output, tristate, or bi directional buffer. input and output signal levels are compatible with the i/o standard selected. during programming, i/os become tristated and weakly pulled up to vcci. with vcci, vmv, and vcc supplies continuously powered up, when the device tr ansitions from programming to operating mode, the i/os are instantly configured to the desired user configuration. unused i/os are configured as follows: ? output buffer is disabled (with tristate value of high impedance) ? input buffer is disabled (with tristate value of high impedance) ? weak pull-up is programmed gl globals gl i/os have access to certain clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the global i/os can be used as regular i/os, since they have identical capabilities. unused gl pins are configured as inputs with pull-up resistors. see more detailed descriptions of global i/o connectivity in the "clock conditioning circuits in low power flash devices and mixed signal fpgas" chapter of the proasic3 nano device family user?s guide . all inputs labeled gc/gf are direct inputs into the quadr ant clocks. for example, if gaa0 is used for an input, gaa1 and gaa2 are no longer available fo r input to the quadrant globals. all inputs labeled gc/gf are direct inputs into the ch ip-level globals, and the rest are connected to the quadrant globals. the inputs to the global network are multiplexed, and only one input can be used as a global input. refer to the i/o structure chapter of the proasic3 nano device family user?s guide for an explanation of the naming of global pins.
proasic3 nano flash fpgas revision 11 3-3 jtag pins low power flash devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). vc c must also be powered for the jtag state machine to operate, even if the device is in bypass mode; vjtag alone is insufficient. both vjtag and vcc to the part must be supplied to allow jtag signals to transition the device. isolating the jtag power supply in a separate i/o bank gives greater flexibility in s upply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned for use, the vjtag pin together with the trst pin could be tied to gnd. tck test clock test clock input for jtag boundary scan, isp, and uj tag. the tck pin does not have an internal pull- up/-down resistor. if jtag is not used, microsemi recommends tying off tck to gnd through a resistor placed close to the fpga pin. this prevents jtag operation in case tms enters an undesired state. note that to operate at all vjtag voltages, 500 ? to 1 k ? will satisfy the requirements. refer to table 3-1 for more in formation. tdi test data input serial input for jtag boundary scan, isp, and ujtag us age. there is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jtag boundary scan, isp, and ujtag usage. tms test mode select the tms pin controls the use of the ieee 1532 boundar y scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trst boundary scan reset pin the trst pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the trst pin. if jtag is not used, an external pull- down resistor could be included to ensure the test access port (tap) is held in reset mode. the resistor values must be chosen from ta b l e 3 - 1 and must satisfy the parallel re sistance value requirement. the values in ta b l e 3 - 1 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a jtag chain. in critical applications, an upset in the jtag circui t could allow entrance to an undesired jtag state. in such cases, microsemi recommends tying off trst to gnd through a resistor placed close to the fpga pin. note that to operate at all vjtag voltages, 500 w to 1 kw will satisfy the requirements. table 3-1 ? recommended tie-off values for the tck and trst pins vjtag tie-off resistance vjtag at 3.3 v 200 ? to 1 k ? vjtag at 2.5 v 200 ? to 1 k ? vjtag at 1.8 v 500 ? to 1 k ? vjtag at 1.5 v 500 ? to 1 k ? notes: 1. equivalent parallel resistance if more than one device is on the jtag chain 2. the tck pin can be pulled up/down. 3. the trst pin is pulled down.
pin descriptions and packaging 3-4 revision 11 special function pins nc no connect this pin is not connected to circuitry within the devic e. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. dc do not connect this pin should not be connected to any signals on the pcb. these pins should be left unconnected. packaging semiconductor technology is constantly shrinking in size while growing in capability and functional integration. to enable next-generation silicon tech nologies, semiconductor packages have also evolved to provide improved performance and flexibility. microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability an d performance. microsemi ic packaging technology efficiently supports high-density fpgas with large-pin- count ball grid arrays (bga s), but is also flexible enough to accommodate stringent form factor requi rements for chip scale packaging (csp). in addition, microsemi offers a variety of packages designed to meet your most dema nding application and economic requirements for today's embedded and mobile systems. related documents user?s guides proasic nano device family user?s guide http://www.microsemi.com/s oc/documents/pa3_nano_ug.pdf packaging the following documents provide packaging information and device selection for low power flash devices. product catalog http://www.microsemi.com/soc /documents/prodcat_pib.pdf lists devices currently recommended for new designs and the packages available for each member of the family. use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. package mechanical drawings http://www.microsemi.com/soc /documents/pckgmechdrwngs.pdf this document contains the package mechanical dr awings for all packages currently or previously supplied by microsemi. use the bookmarks to na vigate to the package mechanical drawings. additional packaging materials: http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx .
revision 11 4-1 4 ? package pin assignments 48-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/produ cts/solutions/package/docs.aspx. notes: 1. this is the bottom view of the package. 2. the die attach paddle of the package is tied to ground (gnd). 48 1 pin 1
package pin assignments 4-2 revision 11 48-pin qfn pin number a3pn010 function 1 gec0/io37rsb1 2 io36rsb1 3 gea0/io34rsb1 4 io22rsb1 5gnd 6vccib1 7 io24rsb1 8 io33rsb1 9 io26rsb1 10 io32rsb1 11 io27rsb1 12 io29rsb1 13 io30rsb1 14 io31rsb1 15 io28rsb1 16 io25rsb1 17 io23rsb1 18 vcc 19 vccib1 20 io17rsb1 21 io14rsb1 22 tck 23 tdi 24 tms 25 vpump 26 tdo 27 trst 28 vjtag 29 io11rsb0 30 io10rsb0 31 io09rsb0 32 io08rsb0 33 vccib0 34 gnd 35 vcc 36 io07rsb0 37 io06rsb0 38 gda0/io05rsb0 39 io03rsb0 40 gdc0/io01rsb0 41 io12rsb1 42 io13rsb1 43 io15rsb1 44 io16rsb1 45 io18rsb1 46 io19rsb1 47 io20rsb1 48 io21rsb1 48-pin qfn pin number a3pn010 function
proasic3 nano flash fpgas revision 11 4-3 48-pin qfn pin number a3pn030z function 1 io82rsb1 2 gec0/io73rsb1 3 gea0/io72rsb1 4 geb0/io71rsb1 5gnd 6 vccib1 7 io68rsb1 8 io67rsb1 9 io66rsb1 10 io65rsb1 11 io64rsb1 12 io62rsb1 13 io61rsb1 14 io60rsb1 15 io57rsb1 16 io55rsb1 17 io53rsb1 18 vcc 19 vccib1 20 io46rsb1 21 io42rsb1 22 tck 23 tdi 24 tms 25 vpump 26 tdo 27 trst 28 vjtag 29 io38rsb0 30 gdb0/io34rsb0 31 gda0/io33rsb0 32 gdc0/io32rsb0 33 vccib0 34 gnd 35 vcc 36 io25rsb0 37 io24rsb0 38 io22rsb0 39 io20rsb0 40 io18rsb0 41 io16rsb0 42 io14rsb0 43 io10rsb0 44 io08rsb0 45 io06rsb0 46 io04rsb0 47 io02rsb0 48 io00rsb0 48-pin qfn pin number a3pn030z function
package pin assignments 4-4 revision 11 68-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . notes: 1. this is the bottom view of the package. 2. the die attach paddle of the package is tied to ground (gnd). pin a1 mark 1 68
proasic3 nano flash fpgas revision 11 4-5 68-pin qfn pin number a3pn015 function 1 io60rsb2 2 io54rsb2 3 io52rsb2 4 io50rsb2 5 io49rsb2 6 gec0/io48rsb2 7 gea0/io47rsb2 8vcc 9gnd 10 vccib2 11 io46rsb2 12 io45rsb2 13 io44rsb2 14 io43rsb2 15 io42rsb2 16 io41rsb2 17 io40rsb2 18 io39rsb1 19 io37rsb1 20 io35rsb1 21 io33rsb1 22 io31rsb1 23 io30rsb1 24 vcc 25 gnd 26 vccib1 27 io27rsb1 28 io25rsb1 29 io23rsb1 30 io21rsb1 31 io19rsb1 32 tck 33 tdi 34 tms 35 vpump 36 tdo 37 trst 38 vjtag 39 io17rsb0 40 io16rsb0 41 gda0/io15rsb0 42 gdc0/io14rsb0 43 io13rsb0 44 vccib0 45 gnd 46 vcc 47 io12rsb0 48 io11rsb0 49 io09rsb0 50 io05rsb0 51 io00rsb0 52 io07rsb0 53 io03rsb0 54 io18rsb1 55 io20rsb1 56 io22rsb1 57 io24rsb1 58 io28rsb1 59 nc 60 gnd 61 nc 62 io32rsb1 63 io34rsb1 64 io36rsb1 65 io61rsb2 66 io58rsb2 67 io56rsb2 68 io63rsb2 68-pin qfn pin number a3pn015 function
package pin assignments 4-6 revision 11 68-pin qfn pin number a3pn020 function 1 io60rsb2 2 io54rsb2 3 io52rsb2 4 io50rsb2 5 io49rsb2 6 gec0/io48rsb2 7 gea0/io47rsb2 8vcc 9gnd 10 vccib2 11 io46rsb2 12 io45rsb2 13 io44rsb2 14 io43rsb2 15 io42rsb2 16 io41rsb2 17 io40rsb2 18 io39rsb1 19 io37rsb1 20 io35rsb1 21 io33rsb1 22 io31rsb1 23 io30rsb1 24 vcc 25 gnd 26 vccib1 27 io27rsb1 28 io25rsb1 29 io23rsb1 30 io21rsb1 31 io19rsb1 32 tck 33 tdi 34 tms 35 vpump 36 tdo 37 trst 38 vjtag 39 io17rsb0 40 io16rsb0 41 gda0/io15rsb0 42 gdc0/io14rsb0 43 io13rsb0 44 vccib0 45 gnd 46 vcc 47 io12rsb0 48 io11rsb0 49 io09rsb0 50 io05rsb0 51 io00rsb0 52 io07rsb0 53 io03rsb0 54 io18rsb1 55 io20rsb1 56 io22rsb1 57 io24rsb1 58 io28rsb1 59 nc 60 gnd 61 nc 62 io32rsb1 63 io34rsb1 64 io36rsb1 65 io61rsb2 66 io58rsb2 67 io56rsb2 68 io63rsb2 68-pin qfn pin number a3pn020 function
proasic3 nano flash fpgas revision 11 4-7 68-pin qfn pin number a3pn030z function 1 io82rsb1 2 io80rsb1 3 io78rsb1 4 io76rsb1 5 gec0/io73rsb1 6 gea0/io72rsb1 7 geb0/io71rsb1 8vcc 9gnd 10 vccib1 11 io68rsb1 12 io67rsb1 13 io66rsb1 14 io65rsb1 15 io64rsb1 16 io63rsb1 17 io62rsb1 18 io60rsb1 19 io58rsb1 20 io56rsb1 21 io54rsb1 22 io52rsb1 23 io51rsb1 24 vcc 25 gnd 26 vccib1 27 io50rsb1 28 io48rsb1 29 io46rsb1 30 io44rsb1 31 io42rsb1 32 tck 33 tdi 34 tms 35 vpump 36 tdo 37 trst 38 vjtag 39 io40rsb0 40 io37rsb0 41 gdb0/io34rsb0 42 gda0/io33rsb0 43 gdc0/io32rsb0 44 vccib0 45 gnd 46 vcc 47 io31rsb0 48 io29rsb0 49 io28rsb0 50 io27rsb0 51 io25rsb0 52 io24rsb0 53 io22rsb0 54 io21rsb0 55 io19rsb0 56 io17rsb0 57 io15rsb0 58 io14rsb0 59 vccib0 60 gnd 61 vcc 62 io12rsb0 63 io10rsb0 64 io08rsb0 65 io06rsb0 66 io04rsb0 67 io02rsb0 68 io00rsb0 68-pin qfn pin number a3pn030z function
package pin assignments 4-8 revision 11 100-pin vqfp note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the top view of the package. 1 100
proasic3 nano flash fpgas revision 11 4-9 100-pin vqfp pin number a3pn030z function 1gnd 2 io82rsb1 3 io81rsb1 4 io80rsb1 5 io79rsb1 6 io78rsb1 7 io77rsb1 8 io76rsb1 9gnd 10 io75rsb1 11 io74rsb1 12 gec0/io73rsb1 13 gea0/io72rsb1 14 geb0/io71rsb1 15 io70rsb1 16 io69rsb1 17 vcc 18 vccib1 19 io68rsb1 20 io67rsb1 21 io66rsb1 22 io65rsb1 23 io64rsb1 24 io63rsb1 25 io62rsb1 26 io61rsb1 27 io60rsb1 28 io59rsb1 29 io58rsb1 30 io57rsb1 31 io56rsb1 32 io55rsb1 33 io54rsb1 34 io53rsb1 35 io52rsb1 36 io51rsb1 37 vcc 38 gnd 39 vccib1 40 io49rsb1 41 io47rsb1 42 io46rsb1 43 io45rsb1 44 io44rsb1 45 io43rsb1 46 io42rsb1 47 tck 48 tdi 49 tms 50 nc 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 io41rsb0 58 io40rsb0 59 io39rsb0 60 io38rsb0 61 io37rsb0 62 io36rsb0 63 gdb0/io34rsb0 64 gda0/io33rsb0 65 gdc0/io32rsb0 66 vccib0 67 gnd 68 vcc 69 io31rsb0 70 io30rsb0 100-pin vqfp pin number a3pn030z function 71 io29rsb0 72 io28rsb0 73 io27rsb0 74 io26rsb0 75 io25rsb0 76 io24rsb0 77 io23rsb0 78 io22rsb0 79 io21rsb0 80 io20rsb0 81 io19rsb0 82 io18rsb0 83 io17rsb0 84 io16rsb0 85 io15rsb0 86 io14rsb0 87 vccib0 88 gnd 89 vcc 90 io12rsb0 91 io10rsb0 92 io08rsb0 93 io07rsb0 94 io06rsb0 95 io05rsb0 96 io04rsb0 97 io03rsb0 98 io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp pin number a3pn030z function
package pin assignments 4-10 revision 11 100-pin vqfp pin number a3pn060 function 1gnd 2 gaa2/io51rsb1 3 io52rsb1 4 gab2/io53rsb1 5 io95rsb1 6 gac2/io94rsb1 7 io93rsb1 8 io92rsb1 9gnd 10 gfb1/io87rsb1 11 gfb0/io86rsb1 12 vcomplf 13 gfa0/io85rsb1 14 vccplf 15 gfa1/io84rsb1 16 gfa2/io83rsb1 17 vcc 18 vccib1 19 gec1/io77rsb1 20 geb1/io75rsb1 21 geb0/io74rsb1 22 gea1/io73rsb1 23 gea0/io72rsb1 24 vmv1 25 gndq 26 gea2/io71rsb1 27 geb2/io70rsb1 28 gec2/io69rsb1 29 io68rsb1 30 io67rsb1 31 io66rsb1 32 io65rsb1 33 io64rsb1 34 io63rsb1 35 io62rsb1 36 io61rsb1 37 vcc 38 gnd 39 vccib1 40 io60rsb1 41 io59rsb1 42 io58rsb1 43 io57rsb1 44 gdc2/io56rsb1 45 gdb2/io55rsb1 46 gda2/io54rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io49rsb0 58 gdc0/io46rsb0 59 gdc1/io45rsb0 60 gcc2/io43rsb0 61 gcb2/io42rsb0 62 gca0/io40rsb0 63 gca1/io39rsb0 64 gcc0/io36rsb0 65 gcc1/io35rsb0 66 vccib0 67 gnd 68 vcc 69 io31rsb0 70 gbc2/io29rsb0 100-pin vqfp pin number a3pn060 function 71 gbb2/io27rsb0 72 io26rsb0 73 gba2/io25rsb0 74 vmv0 75 gndq 76 gba1/io24rsb0 77 gba0/io23rsb0 78 gbb1/io22rsb0 79 gbb0/io21rsb0 80 gbc1/io20rsb0 81 gbc0/io19rsb0 82 io18rsb0 83 io17rsb0 84 io15rsb0 85 io13rsb0 86 io11rsb0 87 vccib0 88 gnd 89 vcc 90 io10rsb0 91 io09rsb0 92 io08rsb0 93 gac1/io07rsb0 94 gac0/io06rsb0 95 gab1/io05rsb0 96 gab0/io04rsb0 97 gaa1/io03rsb0 98 gaa0/io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp pin number a3pn060 function
proasic3 nano flash fpgas revision 11 4-11 100-pin vqfp pin number a3pn060z 1gnd 2 gaa2/io51rsb1 3 io52rsb1 4 gab2/io53rsb1 5 io95rsb1 6 gac2/io94rsb1 7 io93rsb1 8 io92rsb1 9gnd 10 gfb1/io87rsb1 11 gfb0/io86rsb1 12 vcomplf 13 gfa0/io85rsb1 14 vccplf 15 gfa1/io84rsb1 16 gfa2/io83rsb1 17 vcc 18 vccib1 19 gec1/io77rsb1 20 geb1/io75rsb1 21 geb0/io74rsb1 22 gea1/io73rsb1 23 gea0/io72rsb1 24 vmv1 25 gndq 26 gea2/io71rsb1 27 geb2/io70rsb1 28 gec2/io69rsb1 29 io68rsb1 30 io67rsb1 31 io66rsb1 32 io65rsb1 33 io64rsb1 34 io63rsb1 35 io62rsb1 36 io61rsb1 37 vcc 38 gnd 39 vccib1 40 io60rsb1 41 io59rsb1 42 io58rsb1 43 io57rsb1 44 gdc2/io56rsb1 45 gdb2/io55rsb1 46 gda2/io54rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io49rsb0 58 gdc0/io46rsb0 59 gdc1/io45rsb0 60 gcc2/io43rsb0 61 gcb2/io42rsb0 62 gca0/io40rsb0 63 gca1/io39rsb0 64 gcc0/io36rsb0 65 gcc1/io35rsb0 66 vccib0 67 gnd 68 vcc 69 io31rsb0 70 gbc2/io29rsb0 100-pin vqfp pin number a3pn060z 71 gbb2/io27rsb0 72 io26rsb0 73 gba2/io25rsb0 74 vmv0 75 gndq 76 gba1/io24rsb0 77 gba0/io23rsb0 78 gbb1/io22rsb0 79 gbb0/io21rsb0 80 gbc1/io20rsb0 81 gbc0/io19rsb0 82 io18rsb0 83 io17rsb0 84 io15rsb0 85 io13rsb0 86 io11rsb0 87 vccib0 88 gnd 89 vcc 90 io10rsb0 91 io09rsb0 92 io08rsb0 93 gac1/io07rsb0 94 gac0/io06rsb0 95 gab1/io05rsb0 96 gab0/io04rsb0 97 gaa1/io03rsb0 98 gaa0/io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp pin number a3pn060z
package pin assignments 4-12 revision 11 100-pin vqfp pin number a3pn125 function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5 io132rsb1 6 gac2/io131rsb1 7 io130rsb1 8 io129rsb1 9gnd 10 gfb1/io124rsb1 11 gfb0/io123rsb1 12 vcomplf 13 gfa0/io122rsb1 14 vccplf 15 gfa1/io121rsb1 16 gfa2/io120rsb1 17 vcc 18 vccib1 19 gec0/io111rsb1 20 geb1/io110rsb1 21 geb0/io109rsb1 22 gea1/io108rsb1 23 gea0/io107rsb1 24 vmv1 25 gndq 26 gea2/io106rsb1 27 geb2/io105rsb1 28 gec2/io104rsb1 29 io102rsb1 30 io100rsb1 31 io99rsb1 32 io97rsb1 33 io96rsb1 34 io95rsb1 35 io94rsb1 36 io93rsb1 37 vcc 38 gnd 39 vccib1 40 io87rsb1 41 io84rsb1 42 io81rsb1 43 io75rsb1 44 gdc2/io72rsb1 45 gdb2/io71rsb1 46 gda2/io70rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io65rsb0 58 gdc0/io62rsb0 59 gdc1/io61rsb0 60 gcc2/io59rsb0 61 gcb2/io58rsb0 62 gca0/io56rsb0 63 gca1/io55rsb0 64 gcc0/io52rsb0 65 gcc1/io51rsb0 66 vccib0 67 gnd 68 vcc 69 io47rsb0 70 gbc2/io45rsb0 100-pin vqfp pin number a3pn125 function 71 gbb2/io43rsb0 72 io42rsb0 73 gba2/io41rsb0 74 vmv0 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io32rsb0 83 io28rsb0 84 io25rsb0 85 io22rsb0 86 io19rsb0 87 vccib0 88 gnd 89 vcc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 io09rsb0 94 io07rsb0 95 gac1/io05rsb0 96 gac0/io04rsb0 97 gab1/io03rsb0 98 gab0/io02rsb0 99 gaa1/io01rsb0 100 gaa0/io00rsb0 100-pin vqfp pin number a3pn125 function
proasic3 nano flash fpgas revision 11 4-13 100-pin vqfp pin number a3pn125z function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5 io132rsb1 6 gac2/io131rsb1 7 io130rsb1 8 io129rsb1 9gnd 10 gfb1/io124rsb1 11 gfb0/io123rsb1 12 vcomplf 13 gfa0/io122rsb1 14 vccplf 15 gfa1/io121rsb1 16 gfa2/io120rsb1 17 vcc 18 vccib1 19 gec0/io111rsb1 20 geb1/io110rsb1 21 geb0/io109rsb1 22 gea1/io108rsb1 23 gea0/io107rsb1 24 vmv1 25 gndq 26 gea2/io106rsb1 27 geb2/io105rsb1 28 gec2/io104rsb1 29 io102rsb1 30 io100rsb1 31 io99rsb1 32 io97rsb1 33 io96rsb1 34 io95rsb1 35 io94rsb1 36 io93rsb1 37 vcc 38 gnd 39 vccib1 40 io87rsb1 41 io84rsb1 42 io81rsb1 43 io75rsb1 44 gdc2/io72rsb1 45 gdb2/io71rsb1 46 gda2/io70rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io65rsb0 58 gdc0/io62rsb0 59 gdc1/io61rsb0 60 gcc2/io59rsb0 61 gcb2/io58rsb0 62 gca0/io56rsb0 63 gca1/io55rsb0 64 gcc0/io52rsb0 65 gcc1/io51rsb0 66 vccib0 67 gnd 68 vcc 69 io47rsb0 70 gbc2/io45rsb0 100-pin vqfp pin number a3pn125z function 71 gbb2/io43rsb0 72 io42rsb0 73 gba2/io41rsb0 74 vmv0 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io32rsb0 83 io28rsb0 84 io25rsb0 85 io22rsb0 86 io19rsb0 87 vccib0 88 gnd 89 vcc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 io09rsb0 94 io07rsb0 95 gac1/io05rsb0 96 gac0/io04rsb0 97 gab1/io03rsb0 98 gab0/io02rsb0 99 gaa1/io01rsb0 100 gaa0/io00rsb0 100-pin vqfp pin number a3pn125z function
package pin assignments 4-14 revision 11 100-pin vqfp pin number a3pn250 function 1gnd 2 gaa2/io67rsb3 3 io66rsb3 4 gab2/io65rsb3 5 io64rsb3 6 gac2/io63rsb3 7 io62rsb3 8 io61rsb3 9gnd 10 gfb1/io60rsb3 11 gfb0/io59rsb3 12 vcomplf 13 gfa0/io57rsb3 14 vccplf 15 gfa1/io58rsb3 16 gfa2/io56rsb3 17 vcc 18 vccib3 19 gfc2/io55rsb3 20 gec1/io54rsb3 21 gec0/io53rsb3 22 gea1/io52rsb3 23 gea0/io51rsb3 24 vmv3 25 gndq 26 gea2/io50rsb2 27 geb2/io49rsb2 28 gec2/io48rsb2 29 io47rsb2 30 io46rsb2 31 io45rsb2 32 io44rsb2 33 io43rsb2 34 io42rsb2 35 io41rsb2 36 io40rsb2 37 vcc 38 gnd 39 vccib2 40 io39rsb2 41 io38rsb2 42 io37rsb2 43 gdc2/io36rsb2 44 gdb2/io35rsb2 45 gda2/io34rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io33rsb1 58 gdc0/io32rsb1 59 gdc1/io31rsb1 60 io30rsb1 61 gcb2/io29rsb1 62 gca1/io27rsb1 63 gca0/io28rsb1 64 gcc0/io26rsb1 65 gcc1/io25rsb1 66 vccib1 67 gnd 68 vcc 69 io24rsb1 70 gbc2/io23rsb1 71 gbb2/io22rsb1 72 io21rsb1 100-pin vqfp pin number a3pn250 function 73 gba2/io20rsb1 74 vmv1 75 gndq 76 gba1/io19rsb0 77 gba0/io18rsb0 78 gbb1/io17rsb0 79 gbb0/io16rsb0 80 gbc1/io15rsb0 81 gbc0/io14rsb0 82 io13rsb0 83 io12rsb0 84 io11rsb0 85 io10rsb0 86 io09rsb0 87 vccib0 88 gnd 89 vcc 90 io08rsb0 91 io07rsb0 92 io06rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 100-pin vqfp pin number a3pn250 function
proasic3 nano flash fpgas revision 11 4-15 100-pin vqfp pin number a3pn250z function 1gnd 2 gaa2/io67rsb3 3 io66rsb3 4 gab2/io65rsb3 5 io64rsb3 6 gac2/io63rsb3 7 io62rsb3 8 io61rsb3 9gnd 10 gfb1/io60rsb3 11 gfb0/io59rsb3 12 vcomplf 13 gfa0/io57rsb3 14 vccplf 15 gfa1/io58rsb3 16 gfa2/io56rsb3 17 vcc 18 vccib3 19 gfc2/io55rsb3 20 gec1/io54rsb3 21 gec0/io53rsb3 22 gea1/io52rsb3 23 gea0/io51rsb3 24 vmv3 25 gndq 26 gea2/io50rsb2 27 geb2/io49rsb2 28 gec2/io48rsb2 29 io47rsb2 30 io46rsb2 31 io45rsb2 32 io44rsb2 33 io43rsb2 34 io42rsb2 35 io41rsb2 36 io40rsb2 37 vcc 38 gnd 39 vccib2 40 io39rsb2 41 io38rsb2 42 io37rsb2 43 gdc2/io36rsb2 44 gdb2/io35rsb2 45 gda2/io34rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 vpump 53 nc 54 tdo 55 trst 56 vjtag 57 gda1/io33rsb1 58 gdc0/io32rsb1 59 gdc1/io31rsb1 60 io30rsb1 61 gcb2/io29rsb1 62 gca1/io27rsb1 63 gca0/io28rsb1 64 gcc0/io26rsb1 65 gcc1/io25rsb1 66 vccib1 67 gnd 68 vcc 69 io24rsb1 70 gbc2/io23rsb1 71 gbb2/io22rsb1 72 io21rsb1 100-pin vqfp pin number a3pn250z function 73 gba2/io20rsb1 74 vmv1 75 gndq 76 gba1/io19rsb0 77 gba0/io18rsb0 78 gbb1/io17rsb0 79 gbb0/io16rsb0 80 gbc1/io15rsb0 81 gbc0/io14rsb0 82 io13rsb0 83 io12rsb0 84 io11rsb0 85 io10rsb0 86 io09rsb0 87 vccib0 88 gnd 89 vcc 90 io08rsb0 91 io07rsb0 92 io06rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 100-pin vqfp pin number a3pn250z function

revision 11 5-1 5 ? datasheet information list of changes the following table lists critical changes that were made in each revision of the proasic3 nano datasheet. revision changes page revision 11 (january 2013) the "proasic3 nano ordering information" section has been updated to mention "y" as "blank" mentioning "device does not include license to implement ip based on the cryptography research, inc. (cri) patent portfolio" (sar 43219). 1-iii added a note stating " vmv pins must be connected to the corresponding vcci pins. see the "vmvx i/o supply voltage (quiet)" section on page 3-1 for further information. " to table 2-1 ? absolute maximum ratings (sar 38326). 2-1 added a note to table 2-2 recommended operating conditions 1, 2 (sar 43646): the programming temperatur e range supported is t ambient = 0c to 85c. 2-2 the note in table 2-73 ? proasic3 nano ccc/pll specification referring the reader to smartgen was revised to refer instead to the online help associated with the core (sar 42570). 2-57 figure 2-32 ? fifo read and figure 2-33 ? fifo write are new (sar 34847). 2-66 libero integrated design envi ronment (ide) was changed to libero system-on-chip (soc) throughout the document (sar 40288). live at power-up (lapu) has been replaced with ?instant on?. na revision 10 (september 2012) the "security" section was modified to clarify t hat microsemi does not support read- back of programmed data. 1-1 revision 9 (march 2012) the "in-system programming (isp) and security" section and "security" section were revised to clarify that although no existi ng security measures can give an absolute guarantee, microsemi fpgas implement the be st security available in the industry (sar 34668). i , 1-1 notes indicating that a3p015 is not recommended for new designs have been added (sar 36761). notes indicating that nano-z devices are not recommended for use in new designs have been added. the "devices not recommended for new designs" section is new (sar 36702). i - iv the y security option and licensed dpa logo were added to the "proasic3 nano ordering information" section . the trademarked licensed dpa logo identifies that a product is covered by a dpa counter-measur es license from cryptography research (sar 34726). iii corrected the commercial temperature range to reflect a range of 0c to 70c instead of ?20c to 70c in the "proasic3 nano ordering information" , "temperature grade offerings" , and the "speed grade and temperature grade matrix" sections (sar 37097). iii - iv the following sentence was removed from the "advanced architecture" section : "in addition, extensive on-chip programming circuitry enables rapid, single-voltage (3.3 v) programming of igloo nano devices via an ieee 1532 jtag interface" (sar 34688). 1-3 the "specifying i/o states during programming" section is new (sar 34698). 1-7
datasheet information 5-2 revision 11 revision 9 (continued) the reference to guidelines for global spines and versatile rows, given in the "global clock contribution?pclock" section , was corrected to t he "spine architecture" section of the global re sources chap ter in the iproasic3 nano fpga fabric user's guide (sar 34736). 2-9 figure 2-3 has been modified for the din waveform; the rise and fall time label has been changed to t din (37114). 2-13 the notes regarding dr ive strength in the "summary of i/o timing characteristics ? default i/o software settings" section and "3.3 v lvcmos wide range" section tables were revised for clarification. they now state that the minimum drive strength for the default software configuration when run in wide range is 100 a. the drive strength displayed in software is supported in normal range only. for a detailed i/v curve, refer to the ibis models (sar 34759). 2-17 , 2-25 the ac loading figures in the "single-ended i/o characteristics" section were updated to match tables in the "summary of i/o timing c haracteristics ? default i/o software sett ings" section (sar 34888). 2-22 added values for minimum pulse width and removed the frmax row from table 2-67 through ta b l e 2 - 7 2 in the "global tree timing characteristics" section . use the software to determine the frmax for the device you are using (sar 36956). 2-54 through 2-56 table 2-73 ? proasic3 n ano ccc/pll specification was updated. a note was added indicating that when the ccc/pll core is generated by microsemi core generator software, not all delay values of the sp ecified delay increments are available (sar 34823). 2-57 the port names in the sram "timing waveforms" , sram "timing characteristics" tables, figure 2-34 ? fifo reset , and the fifo "timing characteristics" tables were revised to ensure consistency with the software names (sar 35743). reference was made to a new application note, simultaneous read-write operations in dual-port sram for flash-based csocs and fpga s , which covers these cases in detail (sar 34871). 2-60 , 2-63 , 2-67 , 2-69 the "pin descriptions and packaging" chapter has been added (sar 34772). 3-1 july 2010 the versioning system for datasheets has been changed. datasheets are assigned a revision number that increments each time the datasheet is revised. the "proasic3 nano device status" table on page ii indicates the status for each device in the device family. n/a revision 8 (april 2010) references to differential inputs were re moved from the datasheet, since proasic3 nano devices do not support differential inputs (sar 21449). n/a the "proasic3 nano device status" table is new. ii the jtag dc voltage was revised in table 2-2 ? recommended operating conditions 1, 2 (sar 24052). the maximum value for vpump programming voltage (operation mode) was changed from 3.45 v to 3.6 v (sar 25220). 2-2 the highest temperature in table 2-6 ? temperature and voltage derating factors for timing delays was changed to 100oc. 2-5 the typical value for a3pn010 was revised in table 2-7 ? quiescent supply current characteristics . the note was revised to remove the statement that values do not include i/o static contribution. 2-6 revision changes page
proasic3 nano flash fpgas revision 11 5-3 revision 8 (continued) the following tables were updated with available information: table 2-8 summary of i/o input buffer power (per pin) ? default i/o software settings ; table 2-9 summary of i/o output buffer power (per pin) ? default i/o software settings1 ; table 2-10 ? different components contributing to dynamic power consumption in proasic3 nano devices ; table 2-14 ? summary of maximum and minimum dc input and output levels ; table 2-18 ? summary of i/o timing characteristics?software default settings (at 35 pf) ; table 2-19 ? summary of i/o timing characteristics?softwar e default settings (at 10 pf) 2-6 through 2-18 table 2-22 ? i/o weak pull-up/pull-down resistances was revised to add wide range data and correct the formulas in the table notes (sar 21348). 2-19 the text introducing table 2-24 ? duration of short circuit event before failure was revised to state six months at 100 inst ead of three months at 110 for reliability concerns. the row for 110 was removed from the table. 2-20 table 2-26 ? i/o input rise time, fall time, and related i/o reliability was revised to give values with schmitt trigger disabled and enabled (sar 24634). the temperature for reliability was changed to 100oc. 2-21 table 2-33 ? minimum and maximum dc input and output levels for 3.3 v lvcmos wide range and the timing tables in the "single-ended i/o characteristics" section were updated with available information. the timing tables for 3.3 v lvcmos wide range are new. 2-22 the following sentence was deleted from the "2.5 v lvcmos" section : "it uses a 5 v? tolerant input buffer and push-pull output buffer." 2-30 values for t ddrisud and f ddrimax were updated in table 2-62 ? input ddr propagation delays . values for f ddomax were added to table 2-64 ? output ddr propagation delays (sar 23919). 2-46 , 2-48 table 2-67 ? a3pn010 global resource through table 2-70 ? a3pn060 global resource were updated with available information. 2-54 through 2-55 table 2-73 ? proasic3 nan o ccc/pll specification was revised (sar 79390). 2-57 revision changes page
datasheet information 5-4 revision 11 revision changes page revision 7 (jan 2010) product brief advance v0.7 all product tables and pin tables were updated to show clearly that a3pn030 is available only in the z feature at this time, as a3pn030z. the nano-z feature grade devices are designated with a z at the end of the part number. n/a packaging advance v0.6 the "68-pin qfn" and "100-pin vqfp" pin tables for a3pn030 were removed. only the z grade for a3pn030 is available at this time. n/a revision 6 (aug 2009) product brief advance v0.6 packaging advance v0.5 the note for a3pn030 in the "proasic3 nano devices" table was revised. it states a3pn030 is available in the z feature grade only. i the "68-pin qfn" pin table for a3pn030 is new. 3-7 the "48-pin qfn" , "68-pin qfn" , and "100-pin vqfp" pin tables for a3pn030z are new. 4-3 , 4-7 , 4-9 the "100-pin vqfp" pin table for a3pn060z is new. 4-11 the "100-pin vqfp" pin table for a3pn125z is new 4-13 the "100-pin vqfp" pin table for a3pn250z is new. 4-15 revision 5 (mar 2009) product brief advance v0.5 all references to speed grade ?f were removed from this document. n/a the "i/os with advanced i/o standards" section was revised to add definitions of hot-swap and cold-sparing. 1-7 revision 4 (feb 2009) packaging advance v0.4 the "100-pin vqfp" pin table for a3pn030 is new. 3-10 revision 3 (feb 2009) packaging advance v0.3 the "100-pin qfn" section was removed. n/a revision 2 (nov 2008) product brief advance v0.4 the "proasic3 nano devices" table was revised to change the maximum user i/os for a3pn020 and a3pn030. the following table note was removed: "six chip (main) and three quadrant global networks are available for a3pn060 and above." i the qn100 package was removed for all devices. n/a the "device marking" section is new. iii revision 1 (oct 2008) product brief advance v0.3 the a3pn030 device was added to product tables and replaces a3p030 entries that were formerly in the tables. i to iv the "wide range i/o support" section is new. 1-7 the "i/os per package" table was updated to add the following information to table note 4: "for nano devices, the vq100 package is offered in both leaded and rohs-compliant versions. all other packages are rohs-compliant only." ii the "proasic3 nano products available in the z feature grade" section was updated to remove qn100 for a3pn250. iv the "general description" section was updated to give correct information about number of gates and dual-port ram for proasic3 nano devices. 1-1
proasic3 nano flash fpgas revision 11 5-5 revision 1 (cont?d) the device architecture figures, figure 1-3 ? proasic3 nano device architecture overview with two i/o banks (a3pn060 and a3pn125) through figure 1-4 ? proasic3 nano device architecture overview with four i/o banks (a3pn250) , were revised. figure 1-1 ? proasic3 device architecture overview with two i/o banks and no ram (a3pn010 and a3pn030) is new. 1-3 through 1-4 the "pll and ccc" section was revised to include information about ccc-gls in a3pn020 and smaller devices. 1-6 dc and switching characteristics advance v0.2 table 2-2 ? recommended operating conditions 1, 2 was revised to add vmv to the vcci row. the following table note wa s added: "vmv pins must be connected to the corresponding vcci pins." 2-2 the values in table 2-7 ? quiescent supply current characteristics were revised for a3pn010, a3pn015, and a3pn020. 2-6 a table note, "all lvcmos 3.3 v software macros support lvcmos 3.3 v wide range, as specified in the jesd 8-b specification," was added to table 2-14 ? summary of maximum and minimum dc input and output levels , table 2-18 ? summary of i/o timing characteristics?s oftware default se ttings (at 35 pf) , and table 2-19 ? summary of i/o timing characteristics?software default settings (at 10 pf) . 2-16 , 2-18 3.3 v lvcmos wide range was added to table 2-21 ? i/o output buffer maximum resistances 1 and table 2-23 ? i/o short currents iosh/iosl . 2-19 , 2-20 packaging advance v0.2 the "48-pin qfn" pin diagram was revised. 4-2 note 2 for the "48-pin qfn" , "68-pin qfn" , and "100-pin vqfp" pin diagrams was added/changed to "the die attach paddle of the package is tied to ground (gnd)." 4-2 , 4-5 , 4-9 the "100-pin vqfp" pin diagram was revised to move the pin ids to the upper left corner instead of the upper right corner. 4-9 revision changes page
datasheet information 5-6 revision 11 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "proasic3 nano device status" table on page ii , is designated as either "product brief," "advance," "preliminary," or "production." th e definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. production this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. safety critical, life support, and high-reliability applications policy the products described in this advance status document may not have completed the microsemi qualification process. products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult the microsemi soc products group terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the soc products group?s products is available at http://www.microsemi.com/s oc/documents/ort_report.pdf . microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local sales office for additional reliability information.

51700111-11/01.13 ? 2012 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. products incl ude high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquarter ed in aliso viejo, calif. learn more at www.microsemi.com . microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996

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